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许粲昊 (Thomas Canhao Xu)

(358) 2 333 8785
xucanhao@gmail.com
canxu@utu.fi
最近更新:2016年11月

450D, Agora Building
Department of Information Technology
University of Turku
Turku, Finland 20014

基本信息

业余爱好

教育

2008年9月-2012年9月

理学博士

计算机系统实验室,信息科技系,图尔库大学,芬兰

 

2005年9月-2007年7月

工学硕士(成绩:最佳5%)

软件工程,软件学院,浙江大学,中国

 

2001年9月-2005年7月

工学学士(成绩:最佳1%)

计算机及其应用,计算机科学学院,江西师范大学,中国

 

1997年9月-2000年7月

高级中学

江西省赣州市第一中学,中国

 

1994年9月-1997年7月

初级中学

江西省赣州市第六中学,中国

 

1989年9月-1994年7月

小学教育

几所小学,中国

 

工作经验

2013年3月至今

图尔库大学信息科学系

图尔库,芬兰

博士后研究员,讲师(助理教授)

 

2008年9月-2013年3月

图尔库大学,和图尔库计算机科学中心(TUCS)

图尔库,芬兰

研究员

 

不定

宁波人民广播电台,和铂金埃尔默公司

中国,和芬兰

配音演员

 

2006年2月-2008年8月

上海威迅教育科技有限公司

宁波,中国

讲师

 

2005年12月-2006年4月

宁波常洪隧道

宁波,中国

系统分析师

 

2005年11月-2006年1月

宁波电信数据中心控制中心

宁波,中国

助理项目经理

 

2005年9月-2006年7月

浙江大学

宁波,中国

助理网络管理员

 

2005年8月-2006年2月

上海启讯商务咨询有限责任公司

上海,中国

系统工程师

 

奖励

教学和指导

活动

技能

发表文章和书籍

    书籍章节

  1. Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, and Tapio Salakoski;
    On Parallel Online Learning for Adaptive Embedded Systems;
    Advancing Embedded Systems and Real-Time Communications with Emerging Technologies, 2014, Pages 262-281;
    Published by IGI Global, DOI: 10.4018/978-1-4666-6034-2.ch011.
  2. 期刊

  3. Thomas Canhao Xu, and Ville Leppänen;
    PEN: a power law–enhanced network design for high efficiency multicore architecture;
    Concurrency and Computation: Practice and Experience;
    Accepted for publication by John Wiley & Sons, DOI: 10.1002/cpe.3988.
  4.  
  5. Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    PDNOC: Partially Diagonal Network-on-chip for High Efficiency Multicore Systems;
    Concurrency and Computation: Practice and Experience, Volume 27, Issue 4, March 2015, Pages 1054-1067;
    Published by John Wiley & Sons, DOI: 10.1002/cpe.3364.
    SCI/EI: WOS:000350293900018
  6.  
  7. Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, and Hannu Tenhunen;
    Optimal Placement of Vertical Connections in 3D Network-on-Chip;
    Journal of Systems Architecture, Volume 59, Issue 7, August 2013, Pages 441-454;
    Published by Elsevier, DOI: 10.1016/j.sysarc.2013.05.002.
    SCI/EI: WOS:000323405100009
  8.  
  9. Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Tapio Salakoski, and Hannu Tenhunen;
    Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems;
    International Journal of Embedded and Real-Time Communication Systems (IJERTCS), Volume 3, Issue 2, April-June 2012, Pages 73-91;
    Published by IGI Global, DOI: 10.4018/jertcs.2012040104.
  10.  
  11. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    An Optimized Network-on-Chip Design for Data Parallel FFT;
    Procedia Engineering, Volume 30, March 2012, Pages 313-318;
    Published by Elsevier, DOI: 10.1016/j.proeng.2012.01.866.
    SCI/EI: WOS:000314170600040
  12.  
  13. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Exploring DRAM Last Level Cache for 3D Network-on-Chip Architecture;
    Advanced Materials Research, Volume 403-408, November 2011, Pages 4009-4018;
    Published by Trans Tech Publications, DOI: 10.4028/www.scientific.net/AMR.403-408.4009.
    SCI/EI: WOS:000310764702063
  14.  
  15. Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, and Hannu Tenhunen;
    A Study of 3D Network-on-Chip Design for Data Parallel H.264 Coding;
    Microprocessors and Microsystems, Volume 35, Issue 7, October 2011, Pages 603-612;
    Published by Elsevier, DOI: 10.1016/j.micpro.2011.06.009.
    SCI/EI: WOS:000297963000003
  16.  
  17. Masoud Daneshtalab, Masoumeh Ebrahimi, Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    A Generic Adaptive Path-based Routing Method for MPSoCs;
    Journal of Systems Architecture, Volume 57, Issue 1, January 2011, Pages 109-120;
    Published by Elsevier, DOI: 10.1016/j.sysarc.2010.08.002.
    SCI/EI: WOS:000287331600009
  18. Springer LNCS

  19. Thomas Canhao Xu, and Ville Leppänen;
    LUTMap: A dynamic heuristic application mapping algorithm based on lookup tables;
    In Proceedings of the 9th International Conference on Internet and Distributed Computing Systems (IDCS), LNCS 9864, pp.134-146, 28-30 September 2016, Wuhan, China;
    Published by Springer, DOI: 10.1007/978-3-319-45940-0_12.
  20.  
  21. Thomas Canhao Xu, and Ville Leppänen;
    DBFS: Dual Best-First Search mapping algorithm for shared-cache multicore processors;
    In Proceedings of the 15th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), LNCS 9528, pp.185-198, 18-20 November 2015, Zhangjiajie, China;
    Published by Springer, DOI: 10.1007/978-3-319-27119-4_13.
  22.  
  23. Thomas Canhao Xu, and Ville Leppänen;
    Cache- and Communication-aware Application Mapping for Shared-cache Multicore Processors;
    In Proceedings of the 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), LNCS 9017, pp.55-67, 24-27 March 2015, Porto, Portugal;
    Published by Springer, DOI: 10.1007/978-3-319-16086-3_5.
    SCI/EI: WOS:000362516500005
  24.  
  25. Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    PDNOC: An Efficient Partially Diagonal Network-on-Chip Design;
    In Proceedings of the 10th International Conference on Parallel Processing and Applied Mathematics (PPAM), LNCS 8384, pp.513-522, 8-11 September 2013, Warsaw, Poland;
    Published by Springer, DOI: 10.1007/978-3-642-55224-3_48.
    SCI/EI: WOS:000349159200048
  26.  
  27. Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access;
    In Proceedings of the 12th International Conference on Parallel Computing Technologies (PaCT), LNCS 7979, pp.436-441, 30 September-4 October 2013, St. Petersburg, Russia;
    Published by Springer, DOI: 10.1007/978-3-642-39958-9_41.
    SCI/EI: WOS:000333402500041
  28.  
  29. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Study of Hierarchical N-Body Methods for Network-on-Chip Architectures;
    In Proceedings of the 17th International Euro-Par Conference, Parallel Processing Workshops (Euro-Par), LNCS 7156/2012, pp.365-374, 29 August-02 September 2011, Bordeaux, France;
    Published by Springer, DOI: 10.1007/978-3-642-29740-3_41.
  30.  
  31. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors;
    In Proceedings of the 17th International Euro-Par Conference, Parallel Processing Workshops (Euro-Par), LNCS 7155/2012, pp.281-291, 29 August-02 September 2011, Bordeaux, France;
    Published by Springer, DOI: 10.1007/978-3-642-29737-3_32.
  32.  
  33. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    A Minimal Average Accessing Time Scheduler for Multicore Processors;
    In Proceedings of the 11th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), LNCS 7017/2011, pp.287-299, 24-26 October 2011, Melbourne, Australia;
    Published by Springer, DOI: 10.1007/978-3-642-24669-2_28.
    SCI/EI: WOS:000307023000028
  34. 会议和工作组

  35. Thomas Canhao Xu, Jonne Pohjankukka, and Ville Leppänen;
    Analysing and Modelling the On-chip Traffic of Parallel Applications;
    In Proceedings of the 42nd Euromicro Conference on Software Engineering and Advanced Applications (SEAA), pp.275-282, 31 August-2 September 2016, Limassol, Cyprus;
    Published by IEEE, DOI: 10.1109/SEAA.2016.25.
  36.  
  37. Thomas Canhao Xu, and Ville Leppänen;
    An efficient dynamic energy-aware application mapping algorithm for multicore processors;
    In Proceedings of the 6th International Conference on Digital Information Processing and Communications (ICDIPC), pp.119-124, 21-23 April 2016, Beirut, Lebanon;
    Published by IEEE, DOI: 10.1109/ICDIPC.2016.7470803.
  38.  
  39. Thomas Canhao Xu, and Ville Leppänen;
    Analysing Emerging Memory Technologies for Big Data and Signal Processing Applications;
    In Proceedings of the 5th International Conference on Digital Information Processing and Communications (ICDIPC), pp.104-109, 7-9 October 2015, Sierre, Switzerland;
    Published by IEEE, DOI: 10.1109/ICDIPC.2015.7323014.
  40.  
  41. Thomas Canhao Xu, and Ville Leppänen;
    A Cache- and Memory-Aware Mapping Algorithm for Big Data Applications;
    In Proceedings of the 5th International Conference on Digital Information Processing and Communications (ICDIPC), pp.110-115, 7-9 October 2015, Sierre, Switzerland;
    Published by IEEE, DOI: 10.1109/ICDIPC.2015.7323015.
  42.  
  43. Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    Trio: A triple class on-chip network design for efficient multicore processors;
    In Proceedings of the 12th IEEE International Conference on Embedded Software and Systems (ICESS), pp.951-956, 24-26 August 2015, New York, USA;
    to be Published by IEEE, DOI: 10.1109/HPCC-CSS-ICESS.2015.44.
  44.  
  45. Thomas Canhao Xu, Jonne Pohjankukka, Paavo Nevalainen, Ville Leppänen, and Tapio Pahikkala;
    Parallel Applications and On-chip Traffic Distributions: Observation, Implication and Modelling;
    In Proceedings of the 10th International Conference on Software Engineering and Applications (ICSOFT-EA), pp.443-449, 20-22 July 2015, Colmar, France;
    Published by SciTePress, DOI: 10.5220/0005553604430449.
  46.  
  47. Thomas Canhao Xu, Jussi Toivonen, Tapio Pahikkala, and Ville Leppänen;
    BDMap: A Heuristic Application Mapping Algorithm for the Big Data Era;
    In Proceedings of the 2014 IEEE 11th Intl Conf on Ubiquitous Intelligence and Computing and 2014 IEEE 11th Intl Conf on Autonomic and Trusted Computing and 2014 IEEE 14th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), pp.821-828, 9-12 December 2014, Bali, Indonesia;
    Published by IEEE, DOI: 10.1109/UIC-ATC-ScalCom.2014.43.
  48.  
  49. Thomas Canhao Xu, Ville Leppänen, and Martti Forsell;
    Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture;
    In Proceedings of the 14th IEEE International Conference on Computer and Information Technology (CIT), pp.204-211, 11-13 September 2014, Xi'an, China;
    Published by IEEE, DOI: 10.1109/CIT.2014.16.
  50.  
  51. Mohammad Fattah, Amir-Mohammad Rahmani, Thomas Canhao Xu, Anil Kanduri, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    Mixed-Criticality Dynamic Task Mapping for NoC-Based Many-Core Systems;
    In Proceedings of the 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp.458-465, 12-14 February 2014, Torino, Italy;
    Published by IEEE, DOI: 10.1109/PDP.2014.100.
    SCI/EI: WOS:000353964700070
  52.  
  53. Thomas Canhao Xu, Ville Leppänen, and Martti Forsell;
    DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing;
    In Proceedings of the IEEE 11th International Conference on Dependable, Autonomic and Secure Computing (DASC), pp.528-535, 21-22 December 2013, Chengdu, China;
    Published by IEEE, DOI: 10.1109/DASC.2013.119.
    SCI/EI: WOS:000360991500092
  54.  
  55. Thomas Canhao Xu, Tapio Pahikkala, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    Optimized Multicore Architectures for Data Parallel Fast Fourier Transform;
    In Proceedings of the 14th International Conference on Computer Systems and Technologies (CompSysTech), pp.75-82, 28-29 June 2013, Ruse, Bulgaria;
    Published by ACM, DOI: 10.1145/2516775.2516808.
  56.  
  57. Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    MMSoC: A Multi-Layer Multi-Core Storage-on-Chip Design for Systems with High Integration;
    In Proceedings of the 14th International Conference on Computer Systems and Technologies (CompSysTech), pp.67-74, 28-29 June 2013, Ruse, Bulgaria;
    Published by ACM, DOI: 10.1145/2516775.2516800.
  58.  
  59. Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    Evaluate and Optimize Parallel Barnes-Hut Algorithm for Emerging Many-Core Architectures;
    In Proceedings of the 11th International Conference on High Performance Computing and Simulation (HPCS), pp.421-428, 1-5 July 2013, Helsinki, Finland;
    Published by IEEE, DOI: 10.1109/HPCSim.2013.6641449.
  60.  
  61. Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    A High-Efficiency Low-Cost Heterogeneous 3D Network-on-Chip Design;
    In Proceedings of the Fifth International Workshop on Network on Chip Architectures (NoCArc), pp.37-42, 1 December 2012, Vancouver, British Columbia, Canada;
    Published by ACM, DOI: 10.1145/2401716.2401725.
  62.  
  63. Thomas Canhao Xu, Tapio Pahikkala, Antti Airola, Pasi Liljeberg, Juha Plosila, Tapio Salakoski, and Hannu Tenhunen;
    Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips;
    In Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications (HPCC), pp.516-523, 25-27 June 2012, Liverpool, United Kingdom;
    Published by IEEE, DOI: 10.1109/HPCC.2012.76.
    SCI/EI: WOS:000310377500067
  64.  
  65. Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen;
    Exploration of Heuristic Scheduling Algorithms for 3D Multicore Processors;
    In Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), pp.22-31, 15-16 May 2012, Schloss Rheinfels, St. Goar, Germany;
    Published by ACM, DOI: 10.1145/2236576.2236579.
  66.  
  67. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Explorations of Optimal Core and Cache Placements for Chip Multiprocessor;
    In Proceedings of the 29th IEEE Norchip Conference (Norchip), pp.1-6, 14-15 November 2011, Lund, Sweden;
    Published by IEEE, DOI: 10.1109/NORCHP.2011.6126728.
  68.  
  69. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Optimal Memory Controller Placement for Chip Multiprocessor;
    In Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp.217-226, 9-14 October 2011, Taipei, Taiwan;
    Published by ACM, DOI: 10.1145/2039370.2039405.
  70.  
  71. Alexander Wei Yin, Thomas Canhao Xu, Bo Yang, Pasi Liljeberg, and Hannu Tenhunen;
    Change Function of 2D/3D Network-on-Chip;
    In Proceedings of the 11th IEEE International Conference on Computer and Information Technology (CIT), pp.181-188, 31 August-02 September 2011, Pafos, Cyprus;
    Published by IEEE, DOI: 10.1109/CIT.2011.38.
  72.  
  73. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Optimal Number and Placement of Through Silicon Vias in 3D Network-on-Chip;
    In Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.105-110, 13-15 April 2011, Cottbus, Germany;
    Published by IEEE, DOI: 10.1109/DDECS.2011.5783057.
    SCI/EI: WOS:000312912900024
  74.  
  75. Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Tapio Salakoski, and Hannu Tenhunen;
    A Parallel Online Regularized Least-Squares Machine Learning Algorithm for Future Multi-Core Processors;
    In Proceedings of the 2011 International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS), pp.590-599, 5-7 March 2011, Vilamoura, Algarve, Portugal;
    Published by SciTePress.
  76.  
  77. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Process Scheduling for Future Multicore Processors;
    In Proceedings of the 5th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC), pp.15-18, 24-26 January 2011, Heraklion, Crete, Greece;
    Published by ACM, DOI: 10.1145/1930037.1930042.
  78.  
  79. Thomas Canhao Xu, Liang Guang, Alexander Wei Yin, Bo Yang, Pasi Liljeberg, and Hannu Tenhunen;
    An Analysis of Designing 2D/3D Chip Multiprocessor with Different Cache Architecture;
    In Proceedings of the 28th IEEE Norchip Conference (Norchip), pp.1-6, 15-16 November 2010, Tampere, Finland;
    Published by IEEE, DOI: 10.1109/NORCHIP.2010.5669433.
  80.  
  81. Bo Yang, Liang Guang, Thomas Canhao Xu, Alexander Wei Yin, Tero Säntti, and Juha Plosila;
    Multi-application Multi-step Mapping Method for Many-core Network-on-Chips;
    In Proceedings of the 28th IEEE Norchip Conference (Norchip), pp.1-6, 15-16 November 2010, Tampere, Finland;
    Published by IEEE, DOI: 10.1109/NORCHIP.2010.5669454.
  82.  
  83. Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, and Hannu Tenhunen;
    3D Network-on-Chip with On-chip DRAM: An Empirical Analysis for Future Chip Multiprocessor;
    In Proceedings of the 2010 International Conference on Computer, Electrical, and Systems Science, and Engineering (ICCESSE), pp.18-24, 27-29 October 2010, Paris, France;
    Published by WASET.
  84.  
  85. Bo Yang, Liang Guang, Thomas Canhao Xu, Tero Säntti, and Juha Plosila;
    Multi-application Mapping Algorithm for Network-on-Chip Platforms;
    In Proceedings of the 26th IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI), pp.540-544, 17-20 November 2010, Eilat, Israel;
    Published by IEEE, DOI: 10.1109/EEEI.2010.5662160.
  86.  
  87. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    A Study of Through Silicon Via Impact to 3D Network-on-Chip Design;
    In Proceedings of the 2010 International Conference on Electronics and Information Engineering (ICEIE), pp.V1-333-V1-337, 1-3 August 2010, Kyoto, Japan;
    Published by IEEE, DOI: 10.1109/ICEIE.2010.5559865.
  88.  
  89. Bo Yang, Thomas Canhao Xu, Tero Säntti, and Juha Plosila;
    Tree-model Based Mapping for Energy-efficient and Low-latency Network-on-Chip;
    In Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.189-192, 14-16 April 2010, Vienna, Austria;
    Published by IEEE, DOI: 10.1109/DDECS.2010.5491789.
  90.  
  91. Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, and Hannu Tenhunen;
    Operating System Processor Scheduler Design for Future Chip Multiprocessor;
    In Proceedings of the 23rd International Conference on Architecture of Computing Systems (ARCS), pp.1-7, 22-23 February 2010, Hannover, Germany;
    Published by VDE VERLAG, DOI: 10.1145/1930037.1930042.
  92.  
  93. Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, and Hannu Tenhunen;
    A Study of 3D Network-on-Chip Design for Data Parallel H.264 Coding;
    In Proceedings of the 27th IEEE Norchip Conference (Norchip), pp.1-6, 16-17 November 2009, Trondheim, Norway;
    Published by IEEE, DOI: 10.1109/NORCHP.2009.5397851.
  94.  
  95. Alexander Wei Yin, Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Explorations of Honeycomb Topologies for Network-on-Chip;
    In Proceedings of the 6th IFIP International Conference on Network and Parallel Computing (NPC), pp.73-79, 19-21 October 2009, Gold Coast, Australia;
    Published by IEEE, DOI: 10.1109/NPC.2009.34.
    SCI/EI: WOS:000278535100011
  96. 技术报告

  97. Thomas Canhao Xu, Pasi Liljeberg, and Hannu Tenhunen;
    Embedded Software System Architecture for MyGoogle-on-Chip;
    TUCS Technical Report, No.922;
    Published by TUCS.
  98. 书籍

  99. Thomas Canhao Xu;
    Project Case Study, internal book for WNE certificates.
  100.  
  101. Thomas Canhao Xu;
    Linux Advanced Server, internal book for WNE certificates.
  102.  
  103. Thomas Canhao Xu;
    Linux System Administration, internal book for WNE certificates.
  104.  
  105. Thomas Canhao Xu;
    Webpage Design, internal book for WNE certificates.
  106. 论文

  107. Thomas Canhao Xu;
    Hardware/Software Co-design for Multicore Architectures, Doctor thesis.
  108.  
  109. Thomas Canhao Xu;
    Analysis and Improvement of the Linux Reiser4 File System, Master thesis.
  110.  
  111. Thomas Canhao Xu;
    Research and Application of the Routing Protocol in Common Use, Bachelor thesis.
  112.  

会议/演讲

  1. 9th International Conference on Internet and Distributed Computing Systems (IDCS), 28-30 September 2016, Wuhan, China;
  2.  
  3. 42nd Euromicro Conference on Software Engineering and Advanced Applications (SEAA), 31 August - 2 September 2016, Limassol, Cyprus;
  4.  
  5. 14th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), 23-26 August 2016, Tianjin, China;
  6.  
  7. 6th International Conference on Digital Information Processing and Communications (ICDIPC), 21-23 April 2016, Beirut, Lebanon;
  8.  
  9. 15th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), 18-20 November 2015, Zhangjiajie, China;
  10.  
  11. 5th International Conference on Digital Information Processing and Communications (ICDIPC), 7-9 October 2015, Sierre, Switzerland;
  12.  
  13. 12th IEEE International Conference on Embedded Software and Systems (ICESS), 24-26 August 2015, New York, USA;
  14.  
  15. 10th International Conference on Software Engineering and Applications (ICSOFT-EA), 20-22 July 2015, Colmar, France;
  16.  
  17. 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS), 24-27 March 2015, Porto, Portugal;
  18.  
  19. 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 4-6 March 2015, Turku, Finland;
  20.  
  21. 14th IEEE International Conference on Scalable Computing and Communication (ScalCom), 9-12 December 2014, Bali, Indonesia;
  22.  
  23. 14th IEEE International Conference on Computer and Information Technology (CIT), 11-13 September 2014, Xi'an, China;
  24.  
  25. 13th IEEE International Conference on Scalable Computing and Communication (ScalCom), 21-22 December 2013, Chengdu, China;
  26.  
  27. 12th International Conference on Parallel Computing Technologies (PaCT), 30 September-4 October 2013, St. Petersburg, Russia;
  28.  
  29. 10th International Conference on Parallel Processing and Applied Mathematics (PPAM), 8-11 September 2013, Warsaw, Poland;
  30.  
  31. 11th International Conference on High Performance Computing & Simulation (HPCS), 1-5 July 2013, Helsinki, Finland;
  32.  
  33. 14th International Conference on Computer Systems and Technologies (CompSysTech), 28-29 June 2013, Ruse, Bulgaria;
  34.  
  35. 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 1-5 December 2012, Vancouver, British Columbia, Canada;
  36.  
  37. 14th IEEE International Conference on High Performance Computing and Communications (HPCC), 25-27 June 2012, Liverpool, England, UK;
  38.  
  39. 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 15-16 May 2012, Schloss Rheinfels, St. Goar, Germany;
  40.  
  41. 29th IEEE Norchip Conference (Norchip), 14-15 November 2011, Lund, Sweden;
  42.  
  43. 11th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), 24-26 October 2011, Melbourne, Australia;
  44.  
  45. 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 9-14 October 2011, Taipei, Taiwan;
  46.  
  47. 37th European Solid-State Circuits Research Conference (ESSCIRC), and 41st European Solid-State Device Research Conference (ESSDERC), 12-16 September 2011, Helsinki, Finland;
  48.  
  49. 17th International Euro-Par Conference (Euro-Par), 29 August-2 September 2011, Bordeaux, France;
  50.  
  51. 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 13-15 April 2011, Cottbus, Germany;
  52.  
  53. 6th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), 24-26 January 2011, Heraklion, Crete, Greece;
  54.  
  55. 2010 International Conference on Embedded System and Microprocessors (ICESM), 4-5 December 2010, Manila, Philippines;
  56.  
  57. 28th IEEE Norchip Conference (Norchip), 15-16 November 2010, Tampere, Finland;
  58.  
  59. 2010 International Conference on Computer, Electrical, and Systems Science, and Engineering (ICCESSE), 27-29 October 2010, Paris, France;
  60.  
  61. 12nd International Symposium on System-on-Chip (SOC), 28-30 September 2010, Tampere, Finland;
  62.  
  63. ARTIST Summer School Europe 2010, 5-10 September 2010, Autrans (near Grenoble), France;
  64.  
  65. 2010 International Conference on Electronics and Information Engineering (ICEIE), 1-3 August 2010, Kyoto, Japan;
  66.  
  67. 23rd International Conference on Architecture of Computing Systems (ARCS), 22-23 February 2010, Hannover, Germany;
  68.  
  69. 27th IEEE Norchip Conference (Norchip), 16-17 November 2009, Trondheim, Norway;
  70.  

References available upon request.

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