Masoud Daneshtalab

Assistant Professor


Citations: 517
H-index: 13

 

Personal

Back to top

 

Position

  • 2013 - present: Lecturer, Communication Systems, Department of IT, University of TURKU, Finland.
  • 2011 - present: Senior Researcher & Lecturer, Embedded Computer Systems, Department of IT,
                            University of TURKU, Finland.
  • 2008 - 2011: Researcher, Embedded Computer Systems, Department of IT, University of TURKU,
                            Finland.
  • 2006 - 2008: Researcher Assistant, Nanosystems Lab., ECE – University of Tehran, Tehran, Iran.
  • 2006 - 2008: Lecturer, Technical College of Shariaty, Tehran, Iran.

Back to top

 

Education

  • 2008 - 2011: PhD student, Computer Systems, Department of Information Technology, Faculty of Mathematics and Natural Sciences, University of TURKU, Turku, Finland.
  • 2009 - 2011: MBA for PhD student, Business and Innovation Department, Faculty of Economy, University of TURKU, Turku, Finland.
  • 2004 - 2006: MS student, Computer Hardware Engineering, Faculty of ECE, University of Tehran, Tehran, Iran, Total GPA 18/20.00 (3.6/4).
  • 1998 - 2002: BS student, Computer Hardware Engineering, Shahid Bahonar University, Kerman, Iran, Total GPA 16.16/20.00(3.2/4).
  • 1994 - 1998: High School Diploma, Boo-ali High School, Tehran, Iran, Total GPA 16.00/20.00.

Back to top

 

Research Areas/Interest

  • On/off-Chip Interconnection Network

  • Manycore Systems-on-Chip

  • Energy Harvesting

  • Adaptive Power Management & Low Power Digital Design

  • Low Power Digital Design

  • 3D Stack Architectures

  • Neuromorphic Computing

  • Embedded OS (RTOS) & Dynamic Task Allocation

  • Bio-Inspired Computing & Fuzzy Logic Systems
  • Formal Modeling and Verification

 

Back to top

 

Teaching Experiences

Back to top

 

Professional Experiences

  • Technical Activities:

    Supported full chip layout and verification from synthesis to tape-out using Cadence tools (Encounter and Virtuoso) and Synopsis tools (Design Compiler & Prim power). Tape-out experience:

     

  • Academic Activities:
    • Editor Activities for Journals

      - Associate Editor of World Research Journal of Computer Architecture (JCA) - Since 2012

      - Editorial Board of the International Journal of Embedded and Real-Time Communication Systems -
                                  (IJERTCS) - Since 2013

      - Editorial Board of the International Journal of Distributed Systems and Technologies (IJDST) -
                                  Since 2012


      - Guest Editor, Elsevier Journal of Integration, VLSI, On-Chip Parallel and Network-Based
                                  Systems, (2014)– CfP


      - Guest Editor, Elsevier Journal of Microprocessors and Microsystems, Manycore Embedded
                                  Systems, (2014)– CfP


      - Guest Editor, Journal of IET (Computers and Digital Techniques), Emerging On-Chip Networks and
                                  Architectures, (2013)– CfP


      - Guest Editor, Springer Journal of Computing, Special Issue on On-Chip Parallel and Network
                                  Systems, (2013)– CfP


      - Guest Editor, ACM Transactions on Embedded Computing Systems, Special Issue on Design
                                  Challenges for Manycore Processors, (2013)– CfP
       

      - Guest Editor, Elsevier Journal of System Architecture, Special Issue on Network-based
                                  Manycore Embedded Systems, (2012)– CfP


    • Technical Program Committee (TPC)

      - IEEE/ACM Design, Automation, and Test in Europe – DATE (2014)
      - IEEE/ACM Asia and South Pacific Design Automation Conference – ASP-DAC (2014)
      - IEEE/ACM Symposium on Networks-on-Chip – NoCS (2013)
      - IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia – ESTIMedia (2012)
      - IEEE Conference on Computer Architecture & Digital Systems – CADS (2013)
      - ACM Workshop on Network-on-Chip Architectures – NoCArc (2013)
      - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing – EUC (2013)
      - IEEE System-on-Chip Conference – SOCC (2013)
      - IEEE Euromicro Conference on Parallel, Distributed and Network-based Computing – PDP (2013)
      - IEEE Special Session on On-Chip Parallel and Network-Based Systems @ PDP – OCPNBS (2013)
      - IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia – ESTIMedia (2012)
      - IEEE Conference on Embedded Software and Systems – ICESS (2012)
      - ACM Workshop on Network-on-Chip Architectures – NoCArc (2012)
      - ACM Workshop on Context-Awareness for Self-Managing Systems – CASEMANS (2012)
      - IEEE Special Session on On-Chip Parallel and Network-Based Systems @ PDP – OCPNBS (2012)
      - IEEE Euromicro Conference on Parallel, Distributed and Network-based Computing – PDP (2012)
      - IEEE Euromicro Conference on Digital System Design (Special Session: M2APS) – DSD (2012)
      - DATICS Workshop Series – IAENG IMECS, IFIP NPC, IEEE BCFIC (2012)
      - IEEE Conference on Embedded Software and Systems – ICESS (2011)
      - IEEE Conference on Networked Embedded Systems for Enterprise Applications – NESEA (2011)
      - DATICS Workshop Series – IAENG IMECS, IFIP NPC, IEEE BCFIC (2012)
       

    Served as a reviewer for the following journals and conferences:

    • Journal Reviewer


      - IEEE Transactions on Parallel and Distributed Systems (TPDS),
      - IEEE Transaction on Computer-Aided Design (TCAD),
      - IEEE Transaction on Computer (TC),
      - IEEE Transaction on VLSI,
      - IET Computers & Digital Techniques
      - ACM Transaction on Embedded Computing Systems (TECS),
      - ACM Transaction on Design Automation of Electronic Systems(TODAES),
      - Journal of Systems Architecture (JSA-Elsevier),
      - Journal of Computer and System Sciences (JCSS-Elsevier),
      - Cluster Computing (Springer),
      - Computers & Mathematics with Applications (Elsevier),
      - Canadian Journal of Electrical and Computer Engineering,
      - Mechatronics (Elsevier),
      - Journal of Low Power Electronics (JOLPE).


    • Conference Reviewer


      - IEEE/ACM Symposium on Networks-on-Chip – NOCS (2012, 13),
      - IEEE/ACM International Conference on Computer-Aided Design – ICCAD (2012),
      - IEEE/ACM Design, Automation and Test in Europe – DATE (2008, 10),
      - IEEE/IFIP International Conference on VLSI – VLSI-SoC (2010),
      - IEEE Annual Symposium on VLSI – ISVLSI (2009, -10, -11),
      - IEEE International Symposium on Computer Architecture & Digital Systems – CADS (2010, 12),
      - IEEE International Symposium on System-on-Chip – SOC (2009, 2010),
      - IEEE Norchip (2008, -09),
      - IEEE Euromicro Conference on Digital System Design – DSD (2010, 12),
      - IEEE Euromicro Conference on Parallel, Distributed and Network-based Computing – PDP (10 - 13),
      - IEEE Workshop on Reconfigurable Communication System-on-Chip – ReCoSoC (2010 - 12).
      - IEEE International Symposium on Circuits and Systems – ISCAS (2012).

Back to top

 

(Co-)Supervision

  • Current and former PhDs:
    • Marco Ramirez, Reconfigurable Many-Core Embedded Systems, since 2012.
    • Fahimeh Farahnakian, Resource Management in Micro and Micro Architecture, since 2012.
    • Mohammad Fattah, Hierarchical Management of Many-Core Systems, since 2011.

Back to top

 

Publications


  • Edited National Books:
    • [109] Data Structure, Getting ready for MS entrance exam, 2006, KFA, ISBN: 9648180572
    • [108] Computer Architecture, Getting ready for MS entrance exam, 2006, KFA, ISBN: 9648180938
    • [107] Digital Design, Getting ready for MS entrance exam, 2006, KFA, ISBN: 964-509-153-0
    • [106] Operating System, Getting ready for MS entrance exam, 2006, KFA, ISBN: 964-8180-87-3
    • [105] Automata, Getting ready for MS entrance exam, 2006, KFA, ISBN: 964-509-8180-23


  • Edited Special Issues of Journals:
    • [103] T. Mak, M. Palesi, and M. Daneshtalab, "Special Issue on Emerging On-Chip Networks and Architectures," Journal of the Institute of Engineering and Technology (IET - Computers and Digital Techniques), pp. 1-3, 2013. (To appear)

    • [102] M. Daneshtalab, P. Liljeberg, M. Modarressi, and L. S. Indrusiak, "Special Issue on Special issue on network-based many-core embedded systems," Elsevier Journal of Systems Architecture (JSA-elsevier), Vol. 59, No. 9, pp. 691-692, 2013.


  • Book Chapters:
    • [101] M. Daneshtalab and M. Palesi, "Basic Concepts on On-Chip Networks," book chapter in Routing Algorithms in Networks-on-Chip (1st ed.) – Springer (2014).

    • [100] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Path-based Multicast Routing Algorithms for 2D and 3D Mesh Networks," book chapter in Routing Algorithms in Networks-on-Chip (1st ed.) – Springer (2014).

    • [99] M. Ebrahimi and M. Daneshtalab, "Learning-based Routing Algorithms for On Chip Networks," book chapter in Routing Algorithms in Networks-on-Chip (1st ed.) – Springer (2014).


  • Journals:
    • [98] X. Wang, M. Yang, Y. Jiang, T. Mak, M. Daneshtalab, and M. Palesi, "On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation," ACM Transactions on Embedded Computing Systems (ACM TECS), 2014. (To appear)

    • [97] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, J. Flich, and H. Tenhunen, "Path-based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing," IEEE Transaction on Computers  (IEEE TC), Special issue on NOCS, 2013. (to appear)

    • [96] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Cluster-based Topologies for 3D Networks-on-Chip Using Advanced Inter-layer Bus Architecture," Elsevier Journal of Computer and System Sciences (JCSS-elsevier), Vol. 79, No. 4, pp. 475-491, 2013.

    • [95] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "A systematic reordering mechanism for on-chip networks using efficient congestion-aware method," Elsevier Journal of Systems Architecture (JSA-elsevier), Vol. 59, No. 4-5, pp. 213-222, 2013.

    • [94] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Memory-Efficient On-Chip Network with Adaptive Interfaces," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (IEEE-TCAD), Vol. 31, No. 1, pp. 146-159, Jan 2012.

    • [93] M. Daneshtalab, M. Kamali, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, and J. Plosila, "Adaptive Input-output Selection Based On-Chip Router Architecture," Journal of Low Power Electronics (JOLPE), Vol. 8, No. 1, pp. 11-29, 2012.  

    • [92] M. Daneshtalab, M. Ebrahimi, T. C. Xu, P. Liljeberg, and H. Tenhunen, "A Generic Adaptive path-based routing method for MPSoCs," Elsevier Journal of Systems Architecture (JSA-elsevier), Vol. 57, No. 1, pp. 109-120, 2011.

    • [91] P. Lotfi-kamran, A. Rahmani, M. Daneshtalab, A. Afzali-Kusha, Z. Navabi, "EDXY - A Smart Congestion-Aware and Link Failure Tolerant Routing Algorithm for Network-on-Chips," Elsevier Journal of Systems Architecture (JSA-elsevier), Vol. 56, No. 7, pp. 256-264, 2010.

    • [90] M. Daneshtalab, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, "Low distance path-based multicast algorithm in NOCs," Journal of the Institute of Engineering and Technology (IET - Computers and Digital Techniques), Special issue on NoC, Vol. 3, Issue 5,  pp. 430-442, Sep 2009.

    • [89] A. Rahmani, M. Daneshtalab, A. A. Kusha, M. Pedram, "Power Efficient Switches with Dynamic Virtual Channel Allocation for Network-on-Chips," Journal of Low Power Electronics (JOLPE), Vol.5, No. 3, pp. 385–395, 2009.

    • [88] M.H Neishaburi, Mohammad Reza Kakoee, M. Daneshtalab, and Saeed Safari, "HW/SW Architecture for Soft-Error Cancellation in Real-Time Operating System," Journal of the Institute of Electronics, Information and Communication Engineers (IEICE), Vol. 4 (2007) , No. 23, pp. 755-761, 2007.


  • Conferences:

    -- 2013 --

    • [86] M. Ebrahimi, M. Daneshtalab, and J. Plosila, "In-Order Delivery Approach for 3D NoCs," In Proceedings of the 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS), pp. , October 2013, Iran. (30% acceptance rate)

    • [85] M. Ebrahimi, M. Daneshtalab, P. Liljeberg and H. Tenhunen, "Fault-tolerant Method with Distributed Monitoring and Management Technique for 3D Stacked Mesh," In Proceedings of the 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS), pp. , October 2013, Iran. (30% acceptance rate)

    • [84] X. Wang, Z. Li, M. Yang, Y. Jiang, M. Daneshtalab, and T. Mak, "Low Cost, High Performance Dynamic-Programming-Based Adaptive Power Allocation Scheme for Many-Core Architectures in the Dark Silicon Era," In Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTImedia), pp. , October 2013, Canada.

    • [83] J. Carabaρo, F. Dios, M. Daneshtalab, and M. Ebrahimi , "An Exploration of Heterogeneous Systems," in Proceedings of 8th IEEE 8th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-7, July 2013, Germany. (36% acceptance rate)

    • [82] M. Ramirez, M. Daneshtalab, P. Liljeberg and J. Plosila, "Towards a Configurable Many-core Accelerator for FPGA-based Embedded Systems," in Proceedings of 8th IEEE 8th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-4, July 2013, Germany. (36% acceptance rate)

    • [81] G. Georgakarakos, M. Daneshtalab, and J, Plosila, "Efficient Application Mapping in Resource Limited Homogeneous NoC-based Manycore Systems," in Proceedings of 8th IEEE 11th International High Performance Computing & Simulation (HPCS), pp. 207-2012, July 2013, Finland.

    • [80] X. Wang, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, and M. Palesi, "On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation," in Proceedings of 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 1-8, April 2013, US. (25% acceptance rate)

    • [79] M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, "Minimal-Path Fault-Tolerant Approach Using Connection-Retaining Structure in Networks-on-Chip," in Proceedings of 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 1-8, April 2013, US. (25% acceptance rate)

    • [78] M. Fattah, M. Daneshtalab, P. Liljeberg, J. Plosila, "Smart Hill Climbing for Agile Dynamic Mapping in Many-Core Systems," in Proceedings of 50th ACM/IEEE Design Automation Conference (DAC), pp. 39-44, June 2013, USA. (24% acceptance rate)

    • [77] M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen, "CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems," in Proceedings of 16th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 1048-1051, March 2013, France. (24% acceptance rate)

    • [76] M. Ebrahimi, M. Daneshtalab, J. Plosila, "Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy," in Proceedings of 16th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 1601-1604, March 2013, France. (24% acceptance rate)

    • [75] M. Ebrahimi, M. Daneshtalab, J. Plosila, F. Mehdipour, "MD: Minimal path-based Fault-Tolerant Routing in On-Chip Networks," in Proceedings of 18th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 35-40, Jan 2013, Japan. (To appear)(30% acceptance rate)

    • [74] M. Ebrahimi, M. Daneshtalab, J. Plosila, "High Performance Fault-Tolerant Routing Algorithm for NoC-based Many-Core Systems," in Proceedings of 21th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 462-469, Feb. 2013, UK.

    • [73] M. Ebrahimi, X. Chang, M. Daneshtalab, J. Plosila, P. Liljeberg, H. Tenhunen, "DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs," in Proceedings of 21th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 499-503, Feb. 2013, UK.

    • -- 2012 --

    • [72] M. Fattah, M. Ramirez, M. Daneshtalab, P. Liljeberg, and J. Plosila, "CoNA: Dynamic Application Mapping for Congestion Reduction in Many-Core Systems" in Proceedings of 30th IEEE International Conference on Computer Design (ICCD), pp. 364-370, Sept 2012, Canada. (26% acceptance rate)

    • [71] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, J. Plosila, P. Liljeberg, "Adaptive Reinforcement Learning Method for Networks-on-Chip," in Proceedings of 16th IEEE 12th International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS XII), pp. 236-243 , July 2012, Greece. (25% acceptance rate)

    • [70] M. Ebrahimi, M. Daneshtalab, F. Farahnakian, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, "HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks," in Proceedings of 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 19-26, May. 2012, Denmark. (25% acceptance rate)

    • [69] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "CATRA-Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks," in Proceedings of 15th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 320-325, Mar. 2012, Germany. (25% acceptance rate)

    • [68] X. Chang, M. Ebrahimi, M. Daneshtalab, T. Westerlund, J. Plosila, "PARS – An Efficient Congestion-Aware Routing Method for Networks-on-Chip," in Proceedings of 16th IEEE International Symposium on Computer Architecture and Digital Systems (CADS), pp. 166-171, May. 2012, Iran. (24% acceptance rate)

    • [67] M. Ebrahimi, M. Daneshtalab, J. Plosila, H. Tenhunen, "MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip," in Proceedings of 15th IEEE Euromicro Conference On Digital System Design (DSD), pp. 201-206, Sept 2012, Turkey.

    • [66] M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, "Dual Congestion Awareness Scheme in On-Chip Networks," in Proceedings of 3rd IEEE International Conference on Networked Embedded Systems for Every Applications (NESEA), pp. 1-6, Dec. 2012, UK.  

    • [65] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, J. Plosila, and P. Liljeberg, "Optimized Q-learning Model for Distributing Traffic in On-Chip Networks," in Proceedings of 3rd IEEE International Conference on Networked Embedded Systems for Every Applications (NESEA), pp. 1-8, Dec. 2012, UK.

    • [64] M. Daneshtalab, M. Ebrahimi, J. Plosila, "GLB - Efficient Global Load Balancing Method for Moderating Congestion in On-Chip Networks," In proc. of 7th IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-5, July 2012, UK.

    • [63] M. Fattah, M. Ramirez, M. Daneshtalab, P. Liljeberg, J. Plosila, "Transport Layer Aware Design of Network Interface in Many-Core Systems," In proc. of 7th IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-7, July 2012, UK.

    • [62] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "LEAR – A Low-weight and Highly Adaptive Routing Method for Distributing Congestions in On-Chip Networks," in Proceedings of 20th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 520-524, Feb. 2012, Germany.

    • [61] M. Daneshtalab, M. Ebrahimi, J. Plosila, "HIBS-Novel Inter-layer Bus Structure for Stacked Architectures," in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, Jan. 2012, Japan.

    • [60] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Memory-Efficient Logic Layer Communication Platform for 3D-Stacked Memory-on-Processor Architectures," in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-8, Jan. 2012, Japan.

    •  

      -- 2011 --

    • [59] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila "Q-learning based Congestion-aware Routing Algorithm for On-Chip Network," in Proceedings of 2th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp. 1-7, Dec. 2011, Australia.

    • [58] M. Kamali, L. Petre, K. Sere and M. Daneshtalab, "CorreComm: A Formal Hierarchical Framework for Communication Designs," in Proceedings of 2th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp. 1-7, Dec. 2011, Australia.

    • [57] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Exploring Congestion-Aware Methods for Distributing Traffic in On-Chip Networks," in Proceedings of Innovative Computing Technology (INCT), Springer-Verlag: Communications in Computer and Information Science (CCIS), pp. 319-327, Dec. 2011, Iran.

    • [56]  M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Agent-based On-Chip Network Using Efficient Selection Method," in Proceedings of 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 284-289, Oct 2011, Hongkong.  (30% acceptance rate)

    • [55] M. Kamali, L. Petre, K. Sere, and M. Daneshtalab, "Formal Modeling of Multicast Communication in 3D NoCs," in Proceedings of  14th IEEE Euromicro Conference on Digital System Design (DSD), pp. 634-642, Sept 2011, Finland.

    • [54] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "High-Performance On-Chip Network Platform for Memory-on-Processor Architectures," in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-6, June 2011, France. (36% acceptance rate)

    • [53] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Efficient Congestion-Aware Selection Method for On-Chip Networks," in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-4, June 2011, France.

    • [52] M. Fattah, M. Daneshtalab, P. Liljeberg, and J. Plosila, "Exploration of MPSoC Monitoring and Management Systems," in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-3, June 2011, France.

    • [51] M. Dehyadegari, M. Daneshtalab, M. Ebrahimi, J. Plosila, and S. Mohammadi, "An Adaptive Fuzzy Logic-based Routing Algorithm for Networks-on-Chip," in Proceedings of 13th IEEE/NASA-ESA International Conference on Adaptive Hardware and Systems (AHS), pp. 208-214, June 2011, USA. (40% acceptance rate)

    • [50] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Cluster-based Topologies for 3D Stacked Architectures," in Proceedings of ACM International Conference on Computing Frontiers (CF), May 2011, Italy. (29% acceptance rate)

    • [49] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Exploring Partitioning Methods for 3D Networks-on-Chip Utilizing Adaptive Routing Model," in Proceedings of 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 73-80, May 2011, USA. (25% acceptance rate)

    • [48] M. Kamali, L. Petre, and K. Sere, M. Daneshtalab, "Refinement-Based Modeling of 3D NoCs," in Proceedings of 4th International Conference on Fundamentals of Software Engineering (FSEN), Springer-Verlag: Lecture Notes in Computer Science (LNCS), pp. 236-252, April 2011, Iran. (25% acceptance rate for regular papers)

    • [47] M. Mottaghi, M. Daneshtalab, "Using Routing Agents for Improving the Quality of Service in General Purpose Networks," in Proceedings of International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS), pp. 609-613, March 2011, Portugal. 

  • -- 2010 --

    • [46] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "CMIT- A Novel Cluster-based Topology for 3D Stacked Architectures," in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-5, Nov 2010, Germany.

    • [45] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Pipeline-Based Interlayer Bus Structure for 3D Networks-on-Chip," in Proceedings of 15th IEEE International Symposium on Computer Architecture & Digital Systems (CADS), pp. 41-47, Sept 2010, Iran. (28% acceptance rate)

    • [44] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Performance Evaluation of Unicast and Multicast Communication in Three-Dimensional Mesh Architectures," in Proceedings of 15th IEEE International Symposium on Computer Architecture & Digital Systems (CADS), pp. 181-182, Sept 2010, Iran. (28% acceptance rate)

    • [43] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Input-Output Selection Based Router for Networks-on-Chip," in Proceedings of 9th IEEE International Symposium on VLSI (ISVLSI), pp. 92-97, July 2010, Greece. (32% acceptance rate)

    • [42] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "A Low-Latency and Memory-Efficient On-Chip Network," in Proceedings of 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 99-106, May 2010, France.  (25% acceptance rate)

    • [41] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "HAMUM – A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs," in Proceedings of 18th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 525-532, February 2010, Italy. (28.1% acceptance rate)

    • [40] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, H. Tenhunen, "A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing," in Proceedings of 18th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 547-550, February 2010, Italy. (28.1% acceptance rate)

    • [39] M. Rahmani, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "Power-Aware NoC Router Using Central Forecasting-Based Dynamic Virtual Channel Allocation," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3224-3227, May 2010, France.  

    • [38] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Partiotioning Methods for Unicast Multicast Traffic in 3D-NoC Architecture," in Proceedings of 4th IEEE International Symposium Design & Diagnostics of Electronics Circuits & Systems (DDECS), pp. 127-132, April 2010, Austria.

    -- 2009 --

    • [37] M. Ebrahimi, M. Daneshtalab, N. Sreejesh, P. Liljeberg, H. Tenhunen, "Efficient Network Interface Architecture for Network-on-Chips," in Proceedings of 27th IEEE International Nordic Microelectronic Conference (Norchip), pp. 1-4, Nov 2009, Norway.

    • [36] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "An Efficient Unicast/Multicast Routing Protocol for MPSoCs," in Proceedings of 12th IEEE Euromicro Conference On Digital System Design (DSD), pp. 203-206, August 2009, Greece.  

    • [35] M. Ebrahimi, M. Daneshtalab, S. Mohammadi, A. Afzali-Kusha, H. Tenhunen, "An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NOCs," in Proceedings of 12th ACM/IEEE Design, Automation, and Test in Europe Conference (DATE), pp. 1064 - 1069 , April 2009, France. (23.4% acceptance rate)

    • [34] A. M. Rahmani, M. Daneshtalab, A. Afzali-Kusha, “Forecasting-based Dynamic Virtual Channels Allocation for Power Optimization of Network-on- Chips,” iin Proceedings of 22th IEEE International Conference on VLSI Design (VLSID), pp. 151-156, Jan 2009, India. (24.6% acceptance rate)

    -- 2008 --

    • [33] P. Lotfi-Kamran, M. Daneshtalab, Z. Navabi, and C. Lucas, “BARP- A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs to Avoid Congestion,” in Proceedings of 11th ACM/IEEE Design, Automation, and Test in Europe Conference (DATE), pp. 1408-1413, Mar 2008, Germany. (23.7% acceptance rate)

    • [32] A. M. Rahmani, M. Daneshtalab, Ali Afzali-Kusha, and Saeed Safari, “Power Efficient Switches with Dynamic Virtual Channel Allocation for Network-on-Chips,” in Proceedings of 5th International Conference on Innovations in Information Technology (Innovations), pp. 121-125 , Dec 2009, UAE.

    • [31] B. Marvasti, M. Daneshtalab, A. Afzali-Kusha, S. Mohammadi, "PAMPR: Power-Aware and Minimum Path Routing Algorithm for NoCs," in Proceedings of 15th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 418-421, Sep 2008, Malta.   

    -- 2007 --

    • [30] M. Daneshtalab, A. Afzali-Kusha, S. Mohammadi, "Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections," in Proceedings of 20th IEEE International Conference on VLSI Design (VLSID), pp. 546-550, Jan 2007, India. (31.7% acceptance rate)

    • [29] M.H Neishaburi, M. R. Kakoee, M. Daneshtalab, "On-Chip Verification of NoCs Using Assertion Processor," in Proceedings of 10th IEEE Euromicro Conference On Digital System Design (DSD), pp. 535-538, Aug 2007, Germany.

    • [28] M.H Neishaburi, M. R. Kakoee, M. Daneshtalab, S. Safari, Z. Navabi, "A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services," in Proceedings of IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.1 - 4, Apr 2007, Poland.

    • [27] M.H Neishaburi, M. Daneshtalab, M. R. Kakoee, S. Safari, "Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors," in Proceedings of ACS/IEEE International Conference on Computer Systems and Applications (AICCSA), pp. 528-534, May 2007, Jordan.

    • [26] M.H Neishaburi, M. Daneshtalab, M. Nabi, S. Mohammadi, "System Level Voltage Scheduling Technique Using UML-RT Model," in Proceedings of ACS/IEEE International Conference on Computer Systems and Applications (AICCSA), pp. 500-505, May 2007, Jordan.

    • [25] M.H Neishaburi, M. R. Kakoee, M. Daneshtalab, "Assertion Based Design Error Diagnosis for Core-Based SoCs,in Proceedings of IEEE International System-on-Chip Conference (SoCC), pp. 269-272, 2007, Taiwan.

    -- 2006 --

    • [24] M. Daneshtalab, A. Sobhani, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, "NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm," in Proceedings of 17th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 33-38, Sep 2006, USA.  (26.7% acceptance rate)

    • [23] M. Daneshtalab, A. Sobhani, M. D. Mottaghi, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, "Ant Colony Based Routing Architecture for Minimizing HotSpots in NOCs," in Proceedings of 19th ACM/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 56 - 61, Sep 2006, Brazil. (37% acceptance rate)

    • [22] A. Sobhani, M. Daneshtalab, A. Afzali-Kusha, O. Fatemi, and Z. Navabi, "Dynamic Routing Algorithm for Avoiding HotSpots in On-chip Networks," in Proceedings of IEEE International conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), pp. 179-183, Sep 2006, Tunis.

    • [21] A. Pedram, M. Daneshtalab, and S. M. Fakhraie, "An Efficient Parallel Architecture for Matrix Computations," in Proceeding of IEEE International Nordic Microelectronic Conference (Norchip), pp. 171-174, Nov 2006, Sweden.

    • [20] M. Daneshtalab, A. Afzali-Kusha, S. Mohammadi, O. Fatemi, "Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections," in Proceedings of 8th IEEE International Symposium on System-on-Chip (ISSOC), pp. 1-4, Nov 2006, Finland.

    • [19] M. Daneshtalab, A. Pedram, A. Afzali-Kusha, S. Mohammadi, "A New Fair Dynamic Routing Algorithm for Avoiding Hot Spots in NoCs," in Proceedings of IEEE International Symposium on Communications and Information Technologies (ISCIT), pp. 237-241, Oct 2006, Thailand.

    • [18] A. Pedram, M. Daneshtalab, N. Sedaghati, and S. M. Fakhraie, "A High-Performance Memory-Efficient Parallel Hardware for Matrix Computation in Signal Processing Applications," in Proceedings of IEEE International Symposium on Communications and Information Technologies (ISCIT), pp. 473-478, Oct 2006, Thailand.

    • [17] M. D. Mottaghi, A. Naghilou, M. Daneshtalab, A. Afzali-Kusha, and Z. Navabi, "Hot Block Ring Counter: A Low Power Synchronous Ring Counter," in Proceedings of IEEE International Conference o Microelectronics (ICM), pp. 58 - 62, Dec 2006, Saudi Arabia.

    • [16] M. D. Mottaghi, M. Riazati, M. Daneshtalab, "Finding low activity op-code sets using genetic computing," in Proceedings of IEEE International Conference o Microelectronics (ICM), pp. 52-57, Dec 2006, Saudi Arabia.

    • [15] M.H.Neishaburi, M.Hamzeh, M. Daneshtalab, "Voltage Scheduling Technique during System Level Design Using UML-RT Model," in Proceedings of IEEE International Design and Test (IDT), Nov 2006, Dubai.

    • [14] M.H Neishaburi, M. R. Kakoee, M. Daneshtalab, S. Mohammadi, "Novel Approach for System Level Voltage Scheduling Technique," in Proceedings of 14th IEEE Iranian Conference on Electrical Engineering (ICEE), May 2006, Iran.

    • [13] M. Daneshtalab, A. Niknafs, “Priority Link State OSPF routing algorithm,” in Proceedings of National Computer Conference (NCC), Oct 2002, Iran.

 

  • Workshops and PhD Forums:
    • [12] M. Ramirez, M. Daneshtalab, P. Liljeberg, J. Plosila, "NoC-AXI Interface for FPGA-based MPSoC Platforms", in Proceedings of 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Norway, Sept 2012.

    • [11] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, "Logic Layer Communication Platform for 3D-Stacked Memory-on-Processor Architectures," 3D Integration Workshop, The Design, Automation, and Test in Europe conference (DATE), Germany, March 2012.

    • [10] M. Daneshtalab, M. Ebrahimi, J. Plosila, "Efficient Multicast Routing Protocols for Networks-on-Chip," in PhD Forum of Design, Automation, and Test in Europe (DATE), PhD-Forum, Germany, March 2012.

    • [9] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila, "Adaptive Routing Scheme for Networks-on-Chip Using Minimal and Non-miniml Paths," in Proceedings of 19th IFIP/IEEE International Conference on Very Large Scale Integration, (VLSI-SoC), PhD-Forum, pp. 461-462, Oct 2011, HongKong.  

    • [8] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, "A minimal/non-minimal routing algorithm for NoCs to misroute packets around congested areas," in Proc. of Work in Progress Session of the International Conference on Digital System Design (WiP-DSD), Sept 2011, Finland.

    • [7] F. Farahnakian, M. Daneshtalab, P. Liljeberg, J. Plosila, "Efficient On-Chip Network Architecture Using Reinforcement Learning," in Proc. of Work in Progress Session of the International Conference on Digital System Design (WiP-DSD), Sept 2011, Finland.

    • [6] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen, “An Efficient Topology for 3D Stacked Architectures3D Integration Workshop, The Design, Automation, and Test in Europe conference (DATE), France, March 2011.

    • [5] M. Kamali, M. Daneshtalab, L. Petre, and K. Sere, "A Formalization of 3D NoCs," in Proceedings of 9th Nordic Workshop on Programming Theory (NWPT), Nov. 2010, Finland.

    • [4] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "High-Performance TSV Architecture for 3-D ICs," in Proceedings of 9th IEEE International Symposium on VLSI (ISVLSI), PhD-Forum, pp. 467-468, May 2010, Greece.

    • [3] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Performance Analysis of 3D NoCs Partitioning Methods," in Proceedings of 9th IEEE International Symposium on VLSI (ISVLSI), PhD-Forum, pp. 467-468, May 2010, Greece.

    • [2] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, H. Tenhunen, “A Novel Interlayer Bus Architecture for Three-Dimensional Network-on-Chips,” 3D Integration Workshop, The Design, Automation, and Test in Europe conference (DATE), Germany, March 2010.

    • [1] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, “Partitioning Methods for Unicast/Multicast Routings in 3D Mesh NOCs,” 3D Integration Workshop, The Design, Automation, and Test in Europe conference (DATE), Germany, March 2010.

Back to top

 

Research Grants and Awards

  • Research Grant Award for Excellence in Graduate Studies from Ulla Tuominen Foundation, 2011.
  • Research Grant Award for Excellence in Graduate Studies from ST-Micro., 2011.
  • Research Grant Award for Excellence in Graduate Studies from ST-Micro., 2010.
  • 4-year fellowship for Doctoral Degree from Graduate School in Electronics, Telecommunications and Automation (GETA) of Helsinki University of Technology, 2009.
  • Research Grant Award for Excellence in Graduate Studies from Nokia Foundation, 2009.
  • Grant Award for Master thesis from Iran Nanotechnology Initiative Council (INIC), 2006.
  • Grant Award for Master thesis from Iran Telecommunication Research Center (ITRC), 2005.

Back to top

 

Contact

Computer Systems Lab., Department of Information Techology, University of Turku

ICT-Building
Joukahaisenkatu 3-5 B
20520, Turku
Finland

Office Tel: (+358) 2-333-6941

Mobile Tel: (+358) 443463441

Email: masdan@utu.fi

 

Back to top

 

# of visitors:    free html visitor counters