Masoumeh (Azin) Ebrahimi

Senior Researcher at KTH and UTU

masebr@kth.se; masebr@utu.fi

Personal

  • Born on August 25, 1982
  • Nationality: Persian-Finnish

Main Activity Domains

  • Fault-Tolerant and Reliable Many-Core Systems
  • eHealth IoT Applications
  • Machine Learning and Data Analytics in Wearable Devices

Current position

I am holding two positions as the project leader; EU VINNOVA/Marie-Curie and Academy of Finland peojects.
  • Senior Researcher holding 3-year EU VINNOVA/Marie-Curie project at KTH Royal Institute of Technology, Sweden since Jan. 2014
  • Senior Researcher holding 3-year Academy of Finland project at University of Turku, Finland since Sep. 2014.

Education

  • MBA (2011-2015): Business & Innovation Department, University of Turku, Finland.
  • Doctoral Degree (2009-2013): Embedded Computer and Electronic Systems Laboratory, University of Turku, Turku, Finland.
  • Master degree (2007-2009): Computer Engineering, Computer Architecture, University of Science and Research, Tehran, Iran.
  • Bachelor degree (2001-2005): Computer Engineering, Computer Architecture, University of Tehran, Tehran, Iran.

Teaching and Pedagogical Activities

  • Pedagogical Training:
    • Doctoral Supervision, LH207V, KTH, Sweden, 2015. (3 credits)
    • Supervision and Assessment of Degree Project Work in 1st and 2nd Cycle, LH219V, KTH, Sweden, 2016. (3 credits)
    • Teaching and Learning in Higher Education, LH231V, KTH, Sweden, 2016. (7.5 credits)
  • Teaching experience:
    • Co-lecturer of the "Digital Design" course, KTH Royal Institute of Technology, Sweden, 2015 & 2016.
    • Lecturer of the advanced course of "System-on-Chip design", Turku, Finland, 2012 to 2016.
  • Teaching assistant:
    • Advanced course of System-on-Chip design, Turku, Finland, 2010 to 2012.
    • Digital system design lab. (Verilog), University of Tehran, Iran, 2006.

Professional Experiences

  • PhD Thesis Examiner:
    • External examiner of a PhD thesis submitted by Rimpy Bishnoi to MNIT Jaipur, India, 2015.
  • Lead/Guest Editor:
    • Elsevier Journal of Computers and Electrical Engineering Special Issue on: On-Chip Parallel and Network-Based Systems”
    • Lead guest editor in the special Issue on “Fault-Tolerant and Reliable Interconnection Network for Parallel Computing Systems” in the world scientific journal
  • Publicity Chair:
    • PDP 2016, Euromicro international conference on parallel, distributed, and network-based processing
      http://www.pdp2016.org/
    • PDP 2015, Euromicro international conference on parallel, distributed, and network-based processing
      http://www.pdp2015.org/
    • NoCArc 2014, 7th International Workshop on Network on Chip Architectures, held in conjunction with the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47)
      http://www.unikore.it/nocarc/committee.html
  • Technical Program Committee:
    • DTIS 2014 to 2016, International Conference on Design and Technology of Integrated Systems
    • PDP 2013 to 2016 Special Session On-Chip Parallel and Network-Based Systems
    • NoCArc 2012 to 2015, International Workshop on Network on Chip Architecture
    • DMCC 2015 & 2016, International Workshop on Dependable Many-Core Computing
    • MES 2013 to 2016, ACM International Workshop on Manycore Embedded Systems
    • DFT 2015 & 2016, International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
    • VLSI 2014 to 2015, VLSI Design & Embedded Systems Conference: IoT-Building A Smart Connected World
    • AASC 2014, Workshop on Architecture-aware Simulation and Computing
    • ANTIFRAGILE 2014, International Workshop on From Dependable to Resilient, from Resilient to Antifragile Ambients and Systems
    • EUC 2013, The 11th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing
    • NESEA 2012, The 3rd IEEE International Conference on Networked Embedded Systems for Every Application

Invited Talks and Research Visits

  • Invited Talk: Chalmers University of Technology, Sweden, Apr. 2015
  • Invited Talk: Vienna University of Technology, Austria, Nov. 2014
  • Research visit to University of California Irvine, Dec. 2015
  • Short research visit to MIT, Washington State University, and Irvine, Oct. 2014
  • Research visit to KTH Royal Institute of Technology, Sweden, Nov. 2013 - Jan. 2014
  • Research visit to the University of Toronto, Canada, Feb. 2013

Publications

  • Book Chapters:

      [3] M. Ebrahimi, "Reliable and Adaptive Routing Algorithms for 2D and 3D Networks-on-Chip", Book chapter in Routing Algorithms in Networks-on-Chip (1st ed.), Springer, 2013.

      [2] M. Ebrahimi, M. Daneshtalab, "Learning-based Routing Algorithms for on-Chip Networks", Book chapter in Routing Algorithms in Networks-on-Chip (1st ed.), Springer, 2013.

      [1] M. Ebrahimi, M.Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Path-based Multicast Routing for 2D and 3D Mesh Networks", Book chapter in Routing Algorithms in Networks-on-Chip (1st ed.), Springer, 2013.

  • Edited Proceedings:

      [2] M. Ebrahimi, D. Goehringer, M. Daneshtalab, M. Palesi, S. Sonntag, F. Angiolini (Eds.), Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES), Held in conjunction with the 42nd Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), ISBN 978-1-4503-3408-2, 2015.

      [1] M. Daneshtalab, M. Palesi, F. Angiolini, J. Plosila, M. Ebrahimi, (Eds.), Proceedings of the 2nd International Workshop on Many-core Embedded Systems (MES), Held in conjunction with the 41st Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), ISBN 978-1-4503-2822-7, 2014.

  • Edited Special Issues of Journals:

      [1] H. Sarbazi-Azad, N. Bagherzadeh, M. Ebrahimi, M. Daneshtalab (Eds.), Introduction to the Special Section on On-chip parallel and network-based systems. Computers & Electrical Engineering 51, 2016.

  • Journals:

      [16] R. Salamat, M. Khayambashi, N. Bagherzadeh, M. Ebrahimi, "A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs", IEEE Transaction on Computers (IEEE TC), 2016.

      [15] L. Huang, J. Wang, M. Ebrahimi, M. Daneshtalab, X. Zhang, G. Li, and A. Jantsch, "Non-blocking Testing for Network-on-Chip", IEEE Transaction on Computers (IEEE TC), 2015.

      [14] L. Huang, X. Zhang, M. Ebrahimi, and , G. Li, "Tolerating transient illegal turn faults in NoCs", Journal of Microprocessors and Microsystems (MICPRO), 2016.

      [13] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, J. Flich, and H. Tenhunen, "Path-based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing", IEEE Transaction on Computers (IEEE TC), 2012.

      [12] M. Ebrahimi, M.Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Cluster-based Topologies for 3D Networks-on-Chip Using Advanced Inter-layer Bus Architecture", Elsevier Journal of Computer and System Sciences (JCSS-elsevier), 2012.

      [11] M. Daneshtalab, M. Ebrahimi, S. Dytckov, and J. Plosila, "In-Order Delivery Approach for 3D NoCs", The Journal of Supercomputing, (Supercomputing), 2014.

      [10] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, "Adaptive Load Balancing in Learning-based Approaches for many-core embedded systems", Journal of Supercomputing, (Supercomputing), 2014.

      [9] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, "Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs", Journal of Microprocessors and Microsystems, Vol. 38, Issue. 1, pp. 64-75, (MICPRO), 2013.

      [8] M. Ebrahimi, M.Daneshtalab, P. Liljeberg, "A Light-weight Fault-Tolerant Routing Algorithm Tolerating Faulty Links and Routers", Springer journal on Computing (Computing), 2013.

      [7] M. Ebrahimi, "Fully Adaptive Routing Algorithms and Region-based Approaches for 2D and 3D NoCs", IET Computers and Digital Techniques (IET), Vol. 7, Issue. 6, pp. 264-273, 2013.

      [6] M. Ebrahimi, H. Tenhunen, M. Dehyadegari, "Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip”, Journal of Systems Architecture (JSA-elsevier), Vol. 59, Issue. 7, pp. 516-527, 2013.

      [5] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "A systematic reordering mechanism for on-chip networks using efficient congestion-aware method", Elsevier Journal of Systems Architecture (JCSS-elsevier), 2012.

      [4] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Memory-Efficient On-Chip Network with Adaptive Interfaces", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (IEEE-TCAD), Vol. 31, No. 1, pp. 146-159, 2012.

      [3] M. Daneshtalab, M. Kamali, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, and J. Plosila, "Adaptive Input-output Selection Based On-Chip Router Architecture", Journal of Low Power Electronics (JOLPE), Vol. 8, No. 1, pp. 11-29, 2012.

      [2] M. Daneshtalab, M. Ebrahimi, T. C. Xu, P. Liljeberg, and H. Tenhunen, "A Generic Adaptive path-based routing method for MPSoCs", Journal of Systems Architecture (JSA-elsevier), Vol. 57, No. 1, pp. 109-120, 2011.

      [1] M. Daneshtalab, M. Ebrahimi, S. Mohammadi, A. Afzali-Kusha, "Low distance path-based multicast algorithm in NOCs", Journal of the Institute of Engineering and Technology (IET - Computers and Digital Techniques), Special issue on NoC, Vol. 3, Issue 5, pp. 430-442, 2009.

  • Conferences:

      [56] G. Sahebi, A. Majd, M. Ebrahimi, J. Plosila, J. Karimpour, and H. Tenhunen, "SEECC: A Secure and Efficient Elliptic Curve Cryptosystem for E-health Applications", The International Conference on High Performance Computing & Simulation, (HPCS), pp. 492-500, 2016, Netherlands.

      [55] A. Weldezion, M. Ebrahimi, M. Daneshtalab and H. Tenhunen, "Automated Power and Latency Management in Heterogeneous 3D NoCs", in ACM workshop on Network on Chip Architecture, (NoCArC), pp. 33-38, 2015, Dec. US.

      [54] X. Zhang, M. Ebrahimi, L. Huang, G. Li, "Fault-Resilient Routing Unit in NoCs", in IEEE international System-on-Chip conference, (SoCC), pp. , 2015, Mar. China.

      [53] J. Wang, M. Ebrahimi, L. Huang, A. Jantsch, G. Li, "Design of Fault-Tolerant and Reliable Networks-on-Chip", in Proceedings of IEEE Computer Society Annual Symposium on VLSI, (ISVLSI), pp. 545-550, 2015, Mar. France. (*Invited Paper*)

      [52] N. Gupta, M. Kumar, A. Sharma, M. S. Gaur, V. Laxmi, M. Daneshtalab, M. Ebrahimi, "Improved Route Selection Approaches using Q-learning framework for 2D NoCs", in Proceedings of 3rd ACM International Workshop on Many-core Embedded Systems, (MES), pp. 33-40, 2015, June, USA.

      [51] A. Rezaei, M. Daneshtalab, D. Zhao, F. Safaei, X. Wang, M. Ebrahimi, "Dynamic Application Mapping Algorithm for Wireless Network-on-Chip", in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), pp. 421-424, 2015, Mar. Finland.

      [50] X. Zhang, M. Ebrahimi, L. Huang, G. Li, and A. Jantsch, "A Network-Level Solution for Fault Detection, Masking, and Tolerance in NoCs", in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), pp. 365-369, 2015, Mar. Finland.

      [49] R. Salamat, M. Ebrahimi, and N. Bagherzadeh "An Adpative, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on Chip", in Proceedings of 23rd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), pp. , 2015, Mar. Finland.

      [48] R. Alizadeh, M. Saneei, and M. Ebrahimi, "Fault-Tolerant Circular Routing Algorithm for 3D-NoC", in Proceedings of International Congress on Technology, Communication and Knowledge, (ICTCK), pp. 1-7, 2014, Nov. Iran.

      [47] M. Ebrahimi, J. Wang, L. Huang, M. Daneshtalab, and A. Jantsch, "Rescuing Healthy Cores Against Disabled Routers", in Proceedings of the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, (DFT), pp. 98-103, 2014, Oct. Netherlands.

      [46] M. Kumar, V. Laxmi, M. Gaur, M. Daneshtalab, M. Ebrahimi, and M. Zwolinski, "Fault tolerant and highly adaptive routing for 2D NoCs", in Proceedings of the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, (DFT), pp. 104-109, 2014, Oct. Netherlands.

      [45] S. Dytckov, M. Daneshtalab, M. Ebrahimi, H. Anwar, J. Plosila, and H. Tenhunen, "Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks", in Proceedings of 17th IEEE Euromicro Conference on Digital System Design, (DSD), pp. 496-503, 2014, Aug. Italy.

      [44] H. Anwar, M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen, S. dytckov, G. Beltrame, "Parameterized AES-based Crypto Processor for FPGAs", in Proceedings of 17th IEEE Euromicro Conference on Digital System Design, (DSD), pp. 465-472, 2014, Aug. Italy.

      [43] H. Anwar, S. Jafri, S. Dytckov, M. Daneshtalab, M. Ebrahimi, A. Hemani, J. Plosila, H. Tenhunen, G.i Beltrame, "Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures", in Proceedings of 17th IEEE Euromicro Conference on Digital System Design, (DSD), pp. 64-68, 2014, Aug. Italy.

      [42] H. Anwar, M. Daneshtalab, M. Ebrahimi, M. Ramírez, J. Plosila, H. Tenhunen, "Integration of AES on Heterogeneous Many-Core system", in Proceedings of 22nd IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing, (PDP), pp. 424-427, Feb. 2014, Italy.

      [41] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "Fault-tolerant Method with Distributed Monitoring and Management Technique for 3D stacked mesh", in Proceedings of 17th CSI International Symposium on Computer Architecture & Digital Systems, (CADS), pp. 93-95, Oct. 2013, Iran.

      [40] M. Ebrahimi, M. Daneshtalab, and J. Plosila, "In-Order Delivery Approach for 3D NoCs", in Proceedings of 17th CSI International Symposium on Computer Architecture & Digital Systems, (CADS), pp. 87-92, Oct. 2013, Iran.

      [39] J. Carabaño, F. Dios, M. Daneshtalab, and M. Ebrahimi, "An Exploration of Heterogeneous Systems", in Proceedings of 8th IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-7, July 2013, Germany.

      [38] M. Ebrahimi, M. Daneshtalab, J. Plosila, and H. Tenhunen, "Minimal-Path Fault-Tolerant Approach Using Connection-Retaining Structure in Networks-on-Chip", in Proceedings of 7th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 1-8, April 2013, US.

      [37] M. Daneshtalab, M. Ebrahimi, J. Plosila, H. Tenhunen, "CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems", in Proceedings of 16th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 1048-1051, March 2013, France.

      [36] M. Ebrahimi, M. Daneshtalab, J. Plosila, "Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy", in Proceedings of 16th ACM/IEEE Design, Automation, and Test in Europe (DATE), pp. 1601-1604, March 2013, France.

      [35] M. Ebrahimi, M. Daneshtalab, J. Plosila, "High Performance Fault-Tolerant Routing Algorithm for NoC-based Many-Core Systems", in Proceedings of 21th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 462-469, Feb. 2013, UK.

      [34] M. Ebrahimi, X. Chang, M. Daneshtalab, J. Plosila, P. Liljeberg, H. Tenhunen, "DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs," in Proceedings of 21th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 499-503, Feb. 2013, UK.

      [33] M. Ebrahimi, M. Daneshtalab, J. Plosila, F. Mehdipour, "MD: Minimal path-based Fault-Tolerant Routing in On-Chip Networks", in Proceedings of 18th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 35-40, Jan 2013, Japan. 

      [32] M. Ebrahimi, M. Daneshtalab, J. Plosila, H. Tenhunen, "MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip", in Proceedings of 15th IEEE Euromicro Conference On Digital System Design (DSD), pp. 201-206, Sept 2012, Turkey.

      [31] M. Ebrahimi, M. Daneshtalab, J. Plosila, "GLB - Efficient Global Load Balancing Method for Moderating Congestion in On-Chip Networks", in Proceedings of 7th IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-5, July 2012, UK.

      [30] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, J. Plosila, P. Liljeberg, "Adaptive Reinforcement Learning Method for Networks-on-Chip", in Proceedings of 16th IEEE 12th International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS XII), pp. 236-243, July 2012, Greece.

      [29] X. Chang, M. Ebrahimi, M. Daneshtalab, T. Westerlund, J. Plosila, "PARS – An Efficient Congestion-Aware Routing Method for Networks-on-Chip", in Proceedings of 16th IEEE International Symposium on Computer Architecture and Digital Systems (CADS), pp. 166-171, May. 2012, Iran.

      [28] M. Ebrahimi, M. Daneshtalab, F. Farahnakian, P. Liljeberg, J. Plosila, M. Palesi, and H. Tenhunen, "HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks", in Proceedings of 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 19-26, May. 2012, Denmark.

      [27] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks", in Proceedings of 15th ACM/IEEE Design, Automation, and Test in Europe (DATE) pp. 320-325, Mar. 2012, Germany.

      [26] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "LEAR – A Low-weight and Highly Adaptive Routing Method for Distributing Congestions in On-Chip Networks", in Proceedings of 20th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 520-524, Feb. 2012, Germany.

      [25] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Optimized Q-learning model for distributing traffic in on-Chip Networks", in Proceedings of 3th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp. 1-8, Dec. 2012, UK.

      [24] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Dual Congestion Awareness Scheme in On-Chip Networks", in Proceedings of 3th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp. 1-6, Dec. 2012, UK.

      [23] M. Daneshtalab, M. Ebrahimi, J. Plosila, "HIBS-Novel Inter-layer Bus Structure for Stacked Architectures", in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, Jan. 2012, Japan.

      [22] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Memory-Efficient Logic Layer Communication Platform for 3D-Stacked Memory-on-Processor Architectures", in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), pp. 1-8, Jan. 2012, Japan.

      [21] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila, "Q-learning based Congestion-aware Routing Algorithm for On-Chip Network", in Proceedings of 2th IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA), pp. 1-7, Dec. 2011, Australia.

      [20] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Exploring Congestion-Aware Methods for Distributing Traffic in On-Chip Networks", in Proceedings of Innovative Computing Technology (INCT) pp. 319-327, Dec. 2011, Iran.

      [19] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Agent-based On-Chip Network Using Efficient Selection Method", in Proceedings of 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) pp. 284-289, Oct. 2011, Hongkong.

      [18] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "High-Performance On-Chip Network Platform for Memory-on-Processor Architectures", in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) pp. 1-6, June 2011, France.

      [17] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Efficient Congestion-Aware Selection Method for On-Chip Networks", in Proceedings of IEEE International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) pp. 1-4, June 2011, France.

      [16] M. Dehyadegari, M. Daneshtalab, M. Ebrahimi, J. Plosila, and S. Mohammadi, "An Adaptive Fuzzy Logic-based Routing Algorithm for Networks-on-Chip", in Proceedings of 13th IEEE/NASA-ESA International Conference on Adaptive Hardware and Systems (AHS) pp. 208-214, June 2011, USA.

      [15] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Cluster-based Topologies for 3D Stacked Architectures", in Proceedings of ACM International Conference on Computing Frontiers (CF), May 2011, Italy.

      [14] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Exploring Partitioning Methods for 3D Networks-on-Chip Utilizing Adaptive Routing Model", in Proceedings of 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 73-80, May 2011, USA.

      [13] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "CMIT- A Novel Cluster-based Topology for 3D Stacked Architectures", in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), Nov 2010, Germany.

      [12] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Pipeline-Based Interlayer Bus Structure for 3D Networks-on-Chip", in Proceedings of 15th IEEE IEEE International Symposium on Computer Architecture & Digital Systems (CADS), pp.41-47, Sep. 2010, Iran.

      [11] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Performance Evaluation of Unicast and Multicast Communication in Three-Dimensional Mesh Architectures", in Proceedings of 15th IEEE International Symposium on Computer Architecture & Digital Systems (CADS), pp.181-182, Sep. 2010, Iran.

      [10] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "Input-Output Selection Based Router for Networks-on-Chip", in Proceedings of 9th IEEE International Symposium on VLSI (ISVLSI), pp. 92-97, Jul. 2010, Greece.

      [9] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "A Low-Latency and Memory-Efficient On-Chip Network", in Proceedings of 4th IEEE International Symposium on Network-on-Chip (NOCS), pp. 99-106, May 2010, France.

      [8] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Partiotioning Methods for Unicast Multicast Traffic in 3D-NoC Architecture", in Proceedings of 4th IEEE International Symposium Design & Diagnostics of Electronics Circuits & Systems (DDECS), pp. 127-132, Apr. 2010, Austria.

      [7] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "HAMUM – A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs", in Proceedings of 18th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 525-532, Feb. 2010, Italy.

      [6] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, H. Tenhunen, "A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing", in Proceedings of 18th IEEE Euromicro Conference on Parallel, Distributed and Network-Based Computing (PDP), pp. 547-550, Feb. 2010, Italy.

      [5] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen, "High-Performance TSV Architecture for 3-D ICs", in Proceedings of 9th IEEE International Symposium on VLSI (ISVLSI), pp. 467-468, May 2010, Greece.

      [4] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Performance Analysis of 3D NoCs Partitioning Methods", in Proceedings of 9th International Symposium on VLSI (ISVLSI), pp. 467-468, May 2010, Greece.

      [3] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "An Efficient Unicast/Multicast Routing Protocol for MPSoCs", in Proceedings of 12th IEEE Euromicro Conference On Digital System Design (DSD), pp. 203-206, Aug. 2009, Greece.

      [2] M. Ebrahimi, M. Daneshtalab, S. Mohammadi, A. Afzali-Kusha, H. Tenhunen, "An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NOCs", in Proceedings of 12th ACM/IEEE Design, Automation, and Test in Europe Conference (DATE), pp. 1064-1069, April 2009, France.

      [1] M. Ebrahimi, M. Daneshtalab, N. Sreejesh, P. Liljeberg, H. Tenhunen, "Efficient Network Interface Architecture for Network-on-Chips", in Proceedings of 27th IEEE International Nordic Microelectronic Conference (Norchip), pp. 1-4, Nov. 2009, Norway.

  • Workshops and PhD Forums:

      [7] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, "Logic Layer Communication Platform for 3D-Stacked Memory-on-Processor Architectures", 3D Integration Workshop, The Design, Automation, and Test in Europe conference (DATE), March 2012, Germany.

      [6] M. Daneshtalab, M. Ebrahimi, J. Plosila, "Efficient Multicast Routing Protocols for Networks-on-Chip," in PhD Forum of Design, Automation, and Test in Europe (DATE), March 2012, Germany.

      [5] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila, "Adaptive Routing Scheme for Networks-on-Chip Using Minimal and Non-miniml Paths", in Proceedings of 19th IFIP/IEEE International Conference on Very Large Scale Integration, (VLSI-SoC), Oct 2011, HongKong.

      [4] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, "A minimal/non-minimal routing algorithm for NoCs to misroute packets around congested areas", in Proceedings of Work in Progress Session of the International Conference on Digital System Design (WiP-DSD), 2011, Finland.

      [3] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, "An Efficient Topology for 3D Stacked Architectures,” 3D Integration Workshop, Design, Automation, and Test in Europe conference, France, March 2011 (DATE), March 2011, France.

      [2] M. Daneshtalab, M. Ebrahimi, P. Liljeberg, H. Tenhunen, "A Novel Interlayer Bus Architecture for Three-Dimensional Network-on-Chips", 3D Integration Workshop, Design, Automation, and Test conference in Europe (DATE), March 2010, Germany.

      [1] M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen, "Partitioning Methods for Unicast/Multicast Routings in 3D Mesh NOCs", 3D Integration Workshop, Design, Automation, and Test conference in Europe (DATE), March 2010, Germany.

Industrial Experiences

  • R&D group (1 year: 2005-2006): FPGA programming, Wireless and Mobile Communication Company, Tehran, Iran
  • R&D group (1 year: 2006-2007): FPGA programming, Electrical Energy Distribution Company, Mashhad, Iran

Contact

Department of Industrial and Medical Engineering, KTH Royal Institute of Technology, Sweden

Postal address in KTH:
Isafjordsgatan 26, Hiss B, Vån 3
SE-164 40 Kista
Sweden

Office tel.: (+46) 87904180

Email: masebr@kth.se

Department of Information Technology, University of Turku, Finland

Postal address in UTU:
Joukahaisenkatu 3-5 B
20520, Turku
Finland

Office tel.: (+358) 23336941

Email: masebr@utu.fi

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