Resume

	Univ. of Turku, Dept. of Information Technology,
	Laboratory of Electronics & Communication Systems.
	ICT, Joukahaisenkatu 3-5, 5th floor, B 5042, Turku 20520, Finland
	Tel: +358 (2) 333 6954, Fax: +358 (2) 333 6950 Email

Tiberiu Seceleanu, Dr.Tech

Date and place of birth						17.09.1969, Bucharest, Romania.
Gender						Male
Nationality						Romanian
Languages						Romanian, English, French, German (basic level)
Marital status						Married
Academic degree						Doctor of Technology
Current position						Assistant Professor, Dept. of Information Technology, Univ. of Turku, Finland
Address						University of Turku, Department of Information Technology, Electronics and Communication Systems ICT, Joukahaisenkatu 3-5, 5th floor, B 5042, Turku 20520, Finland Phone: +358 2 3336954 (office), +358 40 588 3763 (mobile)

Education
2001		Doctor of Technology, Åbo Akademi, Turku, Finland.
1995		Licentiate of Science, “Politehnica” University of Bucharest, Romania, Department of Electronics and Telecommunications.
1994		Master of Science, “Politehnica” University of Bucharest, Romania, Department of Electronics and Telecommunications. Ranked 9^th of approximately 350 students.

Positions
Jan. 2001 –						Assistant Professor, University of Turku, Finland, Dept. of Information Technology. Leave of absence during Dec. 2002 – July 2003.
Dec. 2002 – July 2003						Senior Researcher. PROMPT2Implementation (Parallel processing dedicated, Rapid Optimized Mapping Platform for Telecom applications to Implementation), a project of ITEA (Information Technology for European Advancement) programme, European Union/TEKES & Nokia.
5^th of June, 2001						Doctoral defense. *Thesis: “Systematic Design of Synchronous Digital Circuits”. Opponent: Professor Axel Jantsch, Royal Institute of Technology, Stockholm, Sweden. Reviewers: Professor Mary Sheeran, Department of Computer Science, Chalmers University of Technology, Göteborg, Sweden. Professor Axel Jantsch,* Department of Electronics, Royal Institute of Technology, Stockholm, Sweden.
Sept. 1996 - Dec. 2000						PhD student / researcher, Åbo Akademi and Turku Centre for Computer Science. Supervisor: Professor Kaisa Sere.
1994 –1996						Assistant, at the Applied Electronics / Computer Systems Chair of the Dept. of Electronics & Telecommunications, “Politehnica” University of Bucharest, Romania. Technical consultant for different companies in Bucharest: computer & networking solutions, custom software applications.
Feb- July 1994						MSc student, University of Patras, Greece. Participating in a project commonly developed by the “Politehnica” Univ. of Bucharest, and the University of Patras. Grant awarded by the TEMPUS programme.

Research topics of interest				Embedded computer systems, with focus on system-on-chip architectures System modeling (concepts, languages, tools) Design methodologies (mostly HW) High level specification and design technique FPGA-based design

Teaching experience
Univ. of Turku (2001-)							Courses on: Formal System Design (2004-). SoC Based Design (2002- ). Signal Processors (2001). HDL Based Design (2001- ).
“Politehnica” Univ. of Bucharest 1994-1996							Laboratories and seminars for: Specialized Processors (programming 80x86 processors and peripheral devices). Computer Networks (mainly Novell networks) Software Engineering (C++ programming)
2004-2006							HDL Based Design – ERASMUS programme.

Thesis committee
2004	Tarvo Raudvere. Verification of Local Design Refinements in a System Design Methodology. Opponent at the Licentiate Thesis defense, Royal Institute of Technology, Stockholm, Sweden.
2003	Mika Vuori. Extending and Applying Module Testbench to ASIC Boundary.. MSc. MSc. Thesis. University of Turku, Finland.
2002	Mikko Inkinen. Data storage in personal handheld communication devices. MSc. Thesis. University of Turku, Finland.

Supervision
Ph.D level
2005-	Lavinia Raicea NOC communication issues. (Polytechnic Univ., Bucharest, main supervisor – prof. C. Radoi).
2002-2004	Tomi Westerlund. Digital systems modeling and verification.
M.Sc. level
2005-2006	Tuomas Lindroth (Univ. of Turku).
2004	Sami Rämö (Univ. of Turku): Hardware / Software Realization of the Segmented Bus Platform.
2004	Farhadur Arifin (Royal Institute of Technology, Stockholm, Sweden): Implementation and Evaluation of Segmented-Bus Architecture.
2003	Iris Ramos (Royal Institute of Technology, Stockholm, Sweden): Statecharts Representation of Action Systems.
2003	Andrei Arakelov (Royal Institute of Technology, Stockholm, Sweden): Segmented Bus Structures in Globally-Asynchronous Locally-Synchronous System-On-Chip Design.
1994–1996	Supervision of 5 students for diploma projects (MSc. degree). Dept. of Electronics & Telecommunications, Bucharest Romania.
On-going projects: ADSOC
Professional Service
Professional affiliation								IEEE Member (since 2005)
Program committee member of								· - System-on-Chip Conference (SOCC 2005- ). - NORCCHIP (2005-) - International Workshop on Software Cybernetics (2006-) - NASA/ESA Conference on Adaptive Hardware and Systems (2007-) - COMPSAC (2007-) - IEEE / IFIP Working International Conference on Software Architecture (2007-) - ACM International Conference on Nano-Networks (2007-)
Conference and journal referee								· - Transactions on Embedded Computing Systems (2006) - IEEE Transactions on Computers (2006) - IEEE Transactions on Circuits and Systems I (2005) - Journal of Systems Architecture (2005, 2006) - NORCHIP (2005-) - System-on-Chip Conference (SOCC 2004- ). - IEEE Transactions on Circuits and Systems I (2004) - Electronics and Telecommunications Research Institute Journal - ETRI (2004) - Design and Test in Europe (DATE - 2004, 2005) - The International Symposium on Signals, Circuits and Systems (ISSCS - 2003, 2005) - The International VLSI Conference (2000) - Nordic Journal of Computing (1999)
Conference organization								- Networking session: Multicore Processing and ARTEMIS (IST 2006 Conference (http://ec.europa.eu/information_society/istevent/2006/cf/network-detail.cfm?id=913) - Session: “Modern On-chip Communication Platforms”. International Symposium on Signals, Circuits and Systems (ISSCS 2005).
Tutorials and invited talks								· - T. Seceleanu. The ADSOC project. ICT Turku, 02.2006. - T. Seceleanu. The SegBus Platform- Architecture and SW Issues. At Carnegie Mellon University, 09.2006. - T. Seceleanu, A. Jantsch, H. Tenhunen. On-chip Distributed Architectures. At System On-Chip Conference, 09.2006. - T. Seceleanu. On-chip Distributed Architectures – The SegBus* Approach*. At Mälardalen University, 01.2007.

Publications
Book chapters
J. Plosila, T. Seceleanu, K. Sere					Formal Communication Modeling and Refinement. In J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, editors, Interconnect-Centric Design for Advanced SoC and NoC, Kluwer, 2004. Pages 315-340.

Journal papers
T. Seceleanu					The SegBus Platform - Architecture and Communication Mechanisms. Journal of Systems Architecture (2006), doi:10.1016/j.sysarc.2006.07.002.
T. Seceleanu, D. Garlan					Developing Adaptive Systems with Synchronized Architectures. The Journal of Systems and Software 79 (2006) 1514–1526
C. Seceleanu, T. Seceleanu.					Synchronization Can Improve Control and Modularity. Journal of Universal Computer Science (J.UCS), Vol. 10, Nr. 10, 2004, pages 1429 - 1468.
J. Plosila, T. Seceleanu, P. Liljeberg.					Implementation of a Self-Timed Segmented Bus. IEEE Design & Test Special Issue on Clockless Design, December 2003. Pages 44-50.
J. Plosila T. Seceleanu.					Aspects of VLSI Design of Synchronous Action Systems. Romanian Journal of Information Science and Technology, Volume 1, No. 4, pp. 353-391. The Publishing House of the Romanian Academy, 1998.

Reviewed conference papers
D. Truscan, T. Seceleanu, H. Tenhunen, J. Lilius.					Towards a Design Methodology for Multiprocessor Platforms. To appear, COMPSAC 2007.
T. Seceleanu, A. Jantsch, H. Tenhunen.					On-Chip Distributed Architectures. Proceedings of the IEEE International System on-chip Conference, Austin, TX, USA, Sept. 2006. Short introduction to the associated tutorial, “On-chip Distributed Architectures”. Pages 329-330.
A.D. Swaminathan, T. Seceleanu.					Interrupt Communication on the SegBus platform. Proceedings of the IEEE International System on-chip Conference, Austin, TX, USA, Sept. 2006. Pages 229-232.
T. Lindroth, R. Lavinia, T. Seceleanu, N. Avessta J. Teuhola					Building a UML Profile for On-Chip Distributed Platforms. COMPSAC 2006. Proceedings of the 30^th Annual International Computer Software and Applications Conference. Chicago USA, 2006. Pages 371-372.
T. Lindroth, N. Avessta, J. Teuhola, T. Seceleanu					Complexity Analysis of H.264 Decoder for FPGA Design. IEEE International Conference on Multimedia & Expo (ICME).
T. Seceleanu, A. Jantsch					Communicating with Synchronized Environments. Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD), Turku, Finland, June 2006. Pages 15-24.
T.Seceleanu, V. Leppänen, J. Suomi, O. Nevalainen					Resource Allocation Methodology for the Segmented Bus Platform. Proceedings of the IEEE International SOC Conference, Washington DC, USA, Sept. 2005. Pages 129-132.
T.Seceleanu, D. Garlan					Synchronized Architectures for Adaptive Systems. Proceedings of the 2^nd International Workshop on Software Cybernetics, in conjunction with COMPSAC 2005, Edinburgh, Scotland, July 25-28, 2005. Pages 146-151.
T. Seceleanu, T. Knuutila, O. Nevalainen					Starvation-Free Arbitration Policies for the Segmented Bus Platform. Proceedings of the International Symposium on Signals, Circuits & Systems - ISSCS'2005, Iasi, Romania. Pages 67-70.
T. Seceleanu, St. Stancescu, V. Lazarescu					Distributed Arbitration for the Segmented Bus Platform. To appear in Proceedings of the International Symposium on Signals, Circuits & Systems - ISSCS'2005, Iasi, Romania. Pages 63-66.
S. Rämö, T. Seceleanu					A SW-HW Implementation of Arbitration Protocols. In Proceedings of the 22^nd NORCHIP Conference, November 2004. Pages 237-240.
T. Seceleanu, St. Stancescu					Arbitration for the Segmented Bus Architecture. In Proceedings of the International Semiconductor Conference (CAS 2004), October 4-6, Sinaia, Romania. Pages 487-490.
C. Seceleanu, T. Seceleanu					Modular Design of Reactive Systems. In Proceedings of the 28^th Annual International Computer Software and Applications Conference, COMPSAC 2004, Hong Kong, September 28-30, 2004. Pages 265-271.
T. Seceleanu					Communication on a Segmented Bus Platform. In Proceedings of the IEEE International SOC Conference, Santa Clara CA USA, Sept. 2004. Pages 205-208.
T. Seceleanu, J. Plosila					Constituent Elements of a Correctness-Preserving UML Design Approach. Proceedings of the Fourth International Conference on Integrated Formal Methods, Canterbury, Kent, England, 2004. Pages 236 – 247.
T. Seceleanu, T. Westerlund					Aspects of Formal and Graphical Design of a Bus System. In Proceedings of the Design Automation and Test in Europe Conference, 2004. Pages 396 - 403.
T. Seceleanu, J. Plosila					Modeling On-Chip Communication. In Proceedings of the International Symposium on System-on-Chip - SOC-2003, Tampere, Finland. Pages 89-92.
T. Westerlund, T. Seceleanu					Formal Analysis of a Local Segmented Bus Arbiter. In Proceedings of the 21^{st NORCHIP} Conference, November 2003. Pages 268-271.
T. Seceleanu, T. Westerlund					Segment Arbiter as Action System. In Proceedings of the International Symposium on Signals, Circuits & Systems - SCS'2003, Iasi, Romania, July 2003. Pages 249-252.
J. Plosila, T. Seceleanu					Specification of an Asynchronous On-Chip Bus. Proceedings of the 4th International Conference on Formal Engineering Methods (ICFEM 2002), October 21-25, 2002, Shanghai, China. Pages 383-395.
T. Seceleanu, J. Plosila					Hierarchical Action Systems. Proceedings of Forum on Design Languages 2002, Marseille, France (Abstract).
T. Seceleanu, J. Plosila, P. Liljeberg					On-Chip Segmented Bus: A Self Timed Approach. In Proceedings of the 15^thIEEE ASIC/SOC Conference, Rochester, New York, September 2002. Pages 216-221.
T. Seceleanu, J. Plosila					Formal Pipeline Design. In Proceedings of the 11^thAdvanced Research Working Conference on Correct Hardware Design and Verification Methods, Livingston Scotland, September 2001. Pages 167-172.
T. Seceleanu, J. Plosila					Pipelined Hardware in Synchronous Action Systems. In Proceedings of the International Symposium on Signals, Circuits & Systems - SCS'2001, Iasi, Romania, July 2001, pages 157-160.
T. Seceleanu, J. Plosila					Formal Representation of Gated Clock Designs. In Proceedings of the 13^thAnnual IEEE International ASIC / SOC Conference Systems-On-Chip in the Internet Age, Washington DC, USA, September 2000, pages 352-356.
J. Plosila, T. Seceleanu					Modeling Synchronous Action Systems. In Proceedings of the 17^thNORCHIP Conference, Oslo, Norway, November 1999, pages 242-248.
T. Seceleanu, S. Holmström					An Action Systems Approach to the FEAL-8 Algorithm. In Proceedings of The 11^th Nordic Workshop on Programming Theory, Uppsala University, Sweden, October 6-8, 1999.
T. Seceleanu					VHDL for Synchronous Action Systems. The International HDL Conference and Exhibition, Santa Clara-CA, April 1999.
T. Seceleanu, J. Plosila					Synchronization of Action Systems. International Symposium on Signals, Circuits & Systems, Iasi, Romania, July 1999.
J. Plosila, T. Seceleanu					Design of Synchronous Action Systems. The 12^th International Conference on VLSI Design, Goa, India, January 1999.

Unreviewed publications
T. Seceleanu, V. Leppänen, J. Suomi, O. Nevalainen					On the Organization of Multisegmented Bus. TUCS technical report 647, December 2004.
T. Westerlund, T. Seceleanu					An UML Profile for Action Systems. TUCS technical report 581, December 2003.
T.Seceleanu, J.Plosila					On-Chip Communication Models. TUCS technical report 562, November 2003.
C. Seceleanu, T. Seceleanu					On Designing for Modularity. TUCS technical report 534, June 2003.
J.Plosila, T. Seceleanu					Formal Specification of an Asynchronous On-Chip Bus. TUCS technical report 461, 2002.
T. Seceleanu, J. Plosila, P. Liljeberg					On-Chip Segmented Bus: A Self-Timed Approach. TUCS technical report 462, 2002.
T.Seceleanu, J.Plosila					Synchronous Pipeline Design in Action Systems. TUCS technical report 403, 2001.
J.Plosila, T. Seceleanu					Synchronization of Action Systems. TUCS technical report 271, 1999.
T. Seceleanu					Implementation of Synchronous Action Systems. TUCS technical report 204, 1998.
J.Plosila, T. Seceleanu					Synchronous Action Systems. TUCS technical report 192, 1998.
J.Plosila, T. Seceleanu					An Asynchronous Linear Predictive Analyzer. TUCS technical report 142, 1997.

Interests			Sports (football), computers, hardware, software.

Research topics of interest

2005-2006

2004

2004

2003

2003

Andrei Arakelov (Royal Institute of Technology, Stockholm, Sweden): Segmented Bus Structures in Globally-Asynchronous Locally-Synchronous System-On-Chip Design.

1994–1996

Supervision of 5 students for diploma projects (MSc. degree). Dept. of Electronics & Telecommunications, Bucharest Romania.

Communicating with Synchronized Environments. Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD), Turku, Finland, June 2006. Pages 15-24.