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Department of Information Technology, University of Turku. Joukahaisenkatu 3-5 B, Turku 20520, Finland. |
+358 (2) 333-7980 Office: ICT building, Room B5087 |
Mohammad Fattah
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OBJECTIVE |
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· Computer architecture. Parallel architectures. · Near-data processing. Massively parallel architectures. · Ultra low power microprocessors. · Bio-inspired processing. Alternative computing paradigms. · Fault-tolerant and fault-aware system design. · Scalable methods for Multi-/Many-core design and management.
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Ph.D., Embedded Electronics |
March 2011—Present |
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University of Turku, Turku, Finland Advisors: Juha Plosila, Pasi Liljeberg, and Hannu Tenhunen Topic: Run-time Resource Management of Many-Core Systems |
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M.Sc., Computer Architecture |
Sept 2007—May 2010 |
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University of Tehran, Tehran, Iran Advisor: Siamak Mohammadi Dissertation Title: “Low Power, Low Latency GALS NoC Design” |
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B.Sc., Hardware Engineering |
Sept 2003—Sept 2007 |
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University of Isfahan, Isfahan, Iran Advisor: Naser Movahedinia Dissertation Title: “Design a USB Interface, using Atmel AVR”
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Research Experiences |
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University of Turku, Turku, Finland Doctoral researcher at Embedded Electronics Lab |
March 2011—Present |
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Advisors: Juha Plosila, Pasi Liljeberg, and Hannu Tenhunen |
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Carnegie Mellon University, Pittsburgh, PA |
Jan 2014—March 2014 |
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Visiting researcher at SFARI research group Visit advisor: Onur Mutlu |
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University of Catania, Catania, Italy |
Oct 2012—Dec 2012 |
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Visiting researcher at Dept. of EECE Visit advisor: Maurizio Palesi |
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University of Tehran, Tehran, Iran |
Oct 2008—May 2010 |
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Researcher at Dependable System Design Lab Advisor: Siamak Mohammadi
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Awards & honors |
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Grant for research and promotion of innovation, Ulla Tuominen Found. PhD forum travel grant, DATE conference |
2015 2015 |
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HiPEAC paper award, for our DAC’14 paper Research grant for excellence in graduate studies, Elisa Found. 4-year fellowship for Doctoral Degree from GETA Graduate School Ranked-31 in nation-wide MSc. entrance exam within 8000 participants Ranked-1400 in nation-wide undergraduate entrance exam within 450,000 participants. Accepted in the first step of nation-wide Mathematics Olympiad
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2014 2012 2011 2007 2003
2000 |
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Teaching & mentorship |
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As Teacher and Lecturer |
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System-on-Chip Design— Graduate level |
Spring 2015 |
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University of Turku, Turku, Finland |
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Multiprocessor Architectures— Graduate level University of Turku, Turku, Finland |
Fall 2014 |
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Computer Architecture— Undergraduate level Islamic Azad University of Najafabad, Najafabad, Iran Computer Architecture Lab— Undergraduate level Islamic Azad University of Najafabad, Najafabad, Iran x86 Assembly Language Basics— Undergraduate level Payame Noor University of Najafabad, Najafabad, Iran AVR/C++ Programming— High school talents Students robotics team, Najafabad, Iran |
Fall 2010
Summer 2010
Spring 2010
Spring, Fall 2005-2006 |
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As Thesis Co-Supervisor |
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Igor Tcarenko—M.Sc. University of Turku, 2015 expected. Kaituo Han—M.Sc. University of Turku & Fudan University, 2015 expected. Yassine Mounir—M.Sc. University of Turku, 2016 expected. |
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As Teaching Assistant |
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HDL-Based Design—Graduate level University of Turku, Turku, Finland. Asynchronous Circuit Design—Graduate level University of Tehran, Tehran, Iran (Spring 2009). Digital Logic Design—Undergraduate level University of Isfahan, Isfahan, Iran (2005-2007). Signals and Systems—Undergraduate level University of Isfahan, Isfahan, Iran (Spring 2007). Operating Systems—Undergraduate level University of Isfahan, Isfahan, Iran (Fall 2006).
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Fall 2011 and 2013
Spring 2009
Fall 2005—2007
Spring 2007
Fall 2006 |
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Publications |
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Please visit http://scholar.google.com/citations?user=4RpclBMAAAAJ for citations. |
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Leading Author [1] M Fattah, A Airola, R Ausavarungnirun, N Mirzaei, P Liljeberg, J Plosila, S Mohammadi, T Pahikkala, O Mutlu and H Tenhunen, “A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips,” In Networks-on-Chip (NOCS), 2015 9th ACM/IEEE International Symposium on, ACM, 2015. [2] M Fattah, M Palesi, P Liljeberg, J Plosila, and H Tenhunen, “SHiFA: System-level hierarchy in run-time fault-aware management of many-core systems,” In Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, pp. 1-6. IEEE, 2014. [3] M Fattah, AM Rahmani, TC Xu, A Kanduri, P Liljeberg, J Plosila, and H Tenhunen, “Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems,” In Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on, pp. 458-465. IEEE, 2014. [4] M Fattah, P Liljeberg, J Plosila, and H Tenhunen, “Adjustable contiguity of run-time task allocation in networked many-core systems,” In Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, pp. 349-354. IEEE, 2014. [5] M Fattah, M Daneshtalab, P Liljeberg, and J Plosila, “Smart Hill Climbing for Agile Dynamic Mapping in Many-Core Systems,” In Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, pp. 1-6. IEEE, 2013. [6] M Fattah, M Ramirez, M Daneshtalab, P Liljeberg, and J Plosila, “CoNA: Dynamic application mapping for congestion reduction in many-core systems,” In Computer Design (ICCD), 2012 IEEE 30th International Conference on, pp. 364-370. IEEE, 2012. [7] M Fattah, M Daneshtalab, P Liljeberg, and J Plosila, “Transport layer aware design of network interface in many-core systems,” In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on, pp. 1-7. IEEE, 2012. [8] M Fattah, M Daneshtalab, P Liljeberg, and J Plosila, “Exploration of MPSoC monitoring and management systems,” In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on, pp. 1-3. IEEE, 2011. [9] M Fattah, A Manian, A Rahimi, and S Mohammadi, “A High Throughput Low Power FIFO Used for GALS NoC Buffers,” In 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 333-338. IEEE, 2010. [10] M Fattah, SA Moghaddam, and S Mohammadi, “A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling,” In Digital System Design, Architectures, Methods and Tools (DSD), 2009 12th Euromicro Conference on, pp. 61-66. IEEE, 2009. Co-Author [11] MH Haghbayan, AM Rahmani, M Fattah, P Liljeberg, J Plosila, Z Navabi, and H Tenhunen, “Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era,” In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. IEEE, 2015. [12] S Holmbacka, M Fattah, W Lund, AM Rahmani, S Lafond, and J Lilius, “A task migration mechanism for distributed many-core operating systems,” The Journal of Supercomputing 68, no. 3 (2014): 1141-1162. [13] I Tcarenko, M Fattah, P Liljeberg, J Plosila, and H Tenhunen, “Multi rectangle modeling approach for application mapping on a many-core system,” In Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on, pp. 452-457. IEEE, 2014. [14] KR Vaddina, AM Rahmani, M Fattah, P Liljeberg, and J Plosila, “Design space exploration of thermal-aware many-core systems” Journal of Systems Architecture 59, no. 10 (2013): 1197-1213. [15] MA Rahimian, S Mohammadi, and M Fattah, “A high-throughput, metastability-free GALS channel based on pausible clock method,” In Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on, pp. 294-300. IEEE, 2010.—Best paper awarded. [16] A Rahimi, ME Salehi, M Fattah, and S Mohammadi, “History-based dynamic voltage scaling with few number of voltage modes for GALS NoC,” In Future Information Technology (FutureTech), 2010 5th International Conference on, pp. 1-6. IEEE, 2010.
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